Senior Manager of Semiconductor Technologies at JRC Integrated Systems

<div class="content-intro"><p></p> <p><strong><span style="color: #333333; font-family: Arial, sans-serif;">Who We Are</span></strong><span style="color: #333333; font-family: Arial, sans-serif;">&nbsp;(<a href="https://bit.ly/3hKrw6h" target="_blank"><span style="color: #337ab7;">video</span></a>)</span></p> <p><span style="color: #333333; font-family: Arial, sans-serif;">At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission-critical microelectronics solutions, aerospace systems engineering, and cutting-edge research and development. By joining JRC, you’ll be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.</span></p> <p></p></div><div>🚀<strong>Join JRC's Semiconductor Technology Team!</strong></div> <div> <p>We are seeking a technically commanding <strong>Senior Manager of Semiconductor Technologies</strong> to manage our core development efforts in radiation-hardened microelectronics. Reporting directly to the Vice President of Semiconductor Technologies, this role oversees the strategic direction and technical execution of our next-generation LEAP Standard Cell Library and leads the development of proprietary simulation software for predicting reliability and radiation-induced error rates.</p> </div> <p><strong>💼What You'll Do</strong></p> <ul> <li><strong>Mentor, manage, and grow</strong> a high-performing multidisciplinary team of device physicists, circuit designers, and software engineers.</li> <li><strong>Serve </strong>as the subject matter expert on Semiconductor Device Physics for radiation effects, including TID, SEE, and SEU.</li> <li><strong>Define </strong>the technical strategy and roadmap for Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.</li> <li><strong>Interface </strong>regularly with government and DoW customers, DIB customers and strategic partners, and attend relevant conferences. Contribute to BD pipeline assessments and capture tracking. Provide hands-on assistance with technical content of capture proposals and work seamlessly with the contracts and proposal execution teams.</li> <li><strong>Direct </strong>the development and enhancement of proprietary software tools used for analyzing circuit reliability and radiation-induced error rates.</li> <li><strong>Oversee </strong>advanced library characterization and simulations to optimize Power, Performance, and Area (PPA) in harsh environments.</li> <li><strong>Manage </strong>relationships with external foundry partners to influence Multi-Product Wafer (MPW) execution and interface directly with customers to ensure technical quality control.</li> </ul> <p><strong>🧠What You Bring</strong></p> <ul> <li>Ph.D. in Electrical Engineering, Applied Physics, or a related field with 2+ years of direct industry experience, OR a Master’s degree with 6+ years of direct industry experience, OR a Bachelor’s degree with 8+ years of experience.</li> <li>Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.</li> <li>Deep foundational knowledge of semiconductor device physics and semiconductor design methodologies and principles.</li> <li>Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)</li> <li>Demonstrated experience being involved in test-chip designs and MPW execution.</li> <li>Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.</li> <li>Extensive experience with semiconductor device &amp; design simulation tools, specifically for library characterization.</li> <li>Demonstrated track record of managing or leading engineers for a minimum of 5 years.</li> <li>Demonstrated end-to-end track record of steering execution of complex technical projects from initial concept/feasibility phase through completion.</li> <li>Outstanding communication and presentation skills</li> </ul> <p><strong>⭐Bonus Points</strong></p> <p></p> <ul> <li>Ph.D. with 5+ years, Master’s with 9+ years, or Bachelor’s with 10+ years of direct industry experience.</li> <li>Proven leadership running and scaling high‑performing multidisciplinary engineering teams while owning technical strategy and roadmaps.</li> <li>Demonstrated success shaping government‑focused proposals/contracts and contributing to BD pipelines and strategic captures.</li> <li>Direct RHBD experience mitigating SEU/SEE, plus proficiency in C++, Python, and TCL for advanced simulation and automation.</li> <li>Hands‑on work with advanced FinFET and GAA nodes (e.g., Intel 18A) and a strong ability to rapidly learn new physics and technology platforms.</li> </ul> <p></p><div class="content-conclusion"><p></p> <p><strong><em>At JRC we offer...</em></strong></p> <ul> <li>A competitive compensation package</li> <li>An exceptional employee benefits program, providing support for our team members' well-being and success</li> <li>The chance to contribute to a high-profile Department of Defense programs and make a positive impact</li> <li>A collaborative work environment where teamwork, creativity, and innovation thrive</li> <li>Opportunities for professional growth and development, helping you advance your career</li> </ul> <p></p></div>