Director, Digital Compute & Power Optimization at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><span data-contrast="auto">Job Description</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">We are looking for a hands-on Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team responsible for delivering the micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs.</span><span data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;201341983&quot;:0,&quot;335551550&quot;:1,&quot;335551620&quot;:1,&quot;335559685&quot;:0,&quot;335559737&quot;:0,&quot;335559738&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}">&nbsp;</span></p> <p><span data-contrast="auto">The ideal candidate should have strong experience with low-power design techniques and a solid understanding of SerDes DSP design, including equalizer optimization for power and area efficiency.</span><span data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;201341983&quot;:0,&quot;335551550&quot;:1,&quot;335551620&quot;:1,&quot;335559685&quot;:0,&quot;335559737&quot;:0,&quot;335559738&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}">&nbsp;</span></p> <p><span data-contrast="auto">The candidate must also have a good knowledge of communication and interface protocols such as CXL/PCIe (Gen 3 and above), Ethernet, or DDR.</span><span data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;201341983&quot;:0,&quot;335551550&quot;:1,&quot;335551620&quot;:1,&quot;335559685&quot;:0,&quot;335559737&quot;:0,&quot;335559738&quot;:0,&quot;335559739&quot;:160,&quot;335559740&quot;:278}">&nbsp;</span></p> <p><strong><span data-contrast="auto">Basic qualifications:</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li><span data-contrast="auto">Strong academic and technical background in electrical engineering. A&nbsp;Bachelor’s&nbsp;degree in EE is&nbsp;required, and a&nbsp;Master’s&nbsp;degree is preferred.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">10+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">5+ years’ experience managing a team of RTL design engineers.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Entrepreneurial, open-mind&nbsp;behavior and can-do attitude. Think and act fast with the customer in mind!</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Authorized to work in Canada and start&nbsp;immediately.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><strong><span data-contrast="auto">Required experience:</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li><span data-contrast="auto">Hands-on, thorough knowledge of high-speed DPSs and SerDes&nbsp;equilizers.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Hands-on, thorough knowledge of high-speed protocols like CXL/PCIe, Ethernet, or DDR.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Proven front end design&nbsp;expertise&nbsp;– architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Experience with Cadence and/or Synopsys digital design tools/flows</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Experience with scripting and automation, with a strong&nbsp;methodology&nbsp;background.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Good knowledge of design for test (DFT), stuck-at and transition scan test insertion</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Familiarity with UVM based design verification</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Silicon&nbsp;bring-up&nbsp;and&nbsp;debug&nbsp;expertise</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Small-geometry CMOS (≤28nm) design</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><strong><span data-contrast="auto">Preferred experience:</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li><span data-contrast="auto">Firmware development with C-language, scripting with Python or other equivalent programming languages.</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Development/support for PCIe or Ethernet Switch products.</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><span data-contrast="auto">The base salary range is CAD 200,000 – CAD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  </span><span data-ccp-props="{}">&nbsp;</span></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>