Staff/ Principal Physical Design CAD Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p><span data-contrast="none"><span class="EOP SCXW38165641 BCX0" data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;335559738&quot;:0,&quot;335559739&quot;:160}">Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a&nbsp;<strong>Physical Design CAD Engineer</strong>&nbsp;with at least&nbsp;<strong>3 years of hands-on experience</strong>&nbsp;in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and&nbsp;<strong>GenAI-based methodologies.</strong></span></span></p> <p data-path-to-node="4">This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.</p> <p data-path-to-node="4"><strong><span data-contrast="none">Key Responsibilities</span></strong></p> <p></p> <div> <p data-olk-copy-source="MessageBody"></p> <div> <p data-olk-copy-source="MessageBody"></p> <div> <div> <p data-olk-copy-source="MessageBody">The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.</p> </div> </div> <div> <div> <p>Key responsibilities include:</p> <ul> <li>Develop and support physical design CAD flows using industry-standard EDA tools</li> <li>Build automation infrastructure for implementation, analysis, reporting, and debug</li> <li>Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification</li> <li>Create scripts and utilities to improve productivity, quality of results, and flow robustness</li> <li>Support and enhance flows based on&nbsp;<strong>Synopsys Fusion Compiler</strong></li> <li>Explore and integrate&nbsp;<strong>GenAI solutions</strong> to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity</li> <li>Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues</li> </ul> </div> </div> </div> </div> <p></p> <p><strong><span data-contrast="none"><br></span>Basic Qualifications</strong></p> <p></p> <p></p> <ul> <li data-olk-copy-source="MessageBody">At least&nbsp;<strong>3 years of experience</strong> in Physical Design, CAD, or implementation methodology</li> <li>Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification</li> <li>Hands-on experience with&nbsp;<strong>Synopsys Fusion Compiler</strong></li> <li>Experience with scripting languages such as&nbsp;<strong>Tcl, Python</strong></li> <li>Ability to develop automation around EDA tools and large-scale design flows</li> <li>Good understanding of timing, power, congestion, floorplanning, and QoR analysis</li> <li>Strong debugging and problem-solving skills</li> <li>Ability to work closely with multiple engineering teams and support complex design environments</li> <li>High motivation to learn and apply&nbsp;<strong>GenAI technologies</strong>&nbsp;in semiconductor design flows.</li> </ul> <p></p> <p><span data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;335559738&quot;:0,&quot;335559739&quot;:160}">&nbsp;</span></p> <p><strong><span data-contrast="none">Preferred Experience</span></strong></p> <p></p> <ul> <li data-olk-copy-source="MessageBody">Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar</li> <li>Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows</li> <li>Experience building dashboards, regression systems, flow checkers, or automated report analyzers</li> <li>Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools</li> <li>Experience with Git, CI/CD, databases, or cloud-based compute environments</li> </ul><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>