Senior Principal Technologist – Memory at Astera Labs
San Jose, California, United StatesFull-timeCTOPosted 24 days ago
Apply with PipelineAbout the Role
<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p>
<p><span data-contrast="none">Are you passionate about pushing the boundaries of system, memory, software, and chip architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera’s development of data center memory solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers’ bottlenecks in hyperscale data centers.</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}"> </span></p>
<p><strong><span data-contrast="none">This role is fully in person, in San Jose. Some travel may be required.</span></strong><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}"> </span></p>
<p><strong><span data-contrast="none">Basic qualifications</span></strong><span data-contrast="none"> </span> </p>
<ul>
<li><span data-contrast="none">BS in Electrical or computer engineering, MS or PhD preferred. </span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}"> </span></li>
<li><span data-contrast="none">≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers </span> </li>
<li>Deep experience with PCIe 5/6, and CXL including protocol level depth </li>
<li>Expertise in OS software integration including memory allocation/management </li>
<li>Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc) </li>
<li>Deep expertise and understanding of memory components (DRAM, etc) </li>
<li>Strong understanding of datacenter system architecture and design challenges </li>
<li>Strong understanding of “full stack” solutions from silicon to application integration </li>
<li>Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases </li>
<li>Ability to dig deeply into technical challenges and use cases </li>
<li>Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners. </li>
<li>Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment. </li>
<li>Willingness to travel occasionally for customer meetings and industry events.<span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}"> </span></li>
</ul>
<p><strong><span data-contrast="none">Preferred experience</span></strong><span data-contrast="none"> </span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Expertise in JEDEC-defined memory interface specifications</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Expertise in memory ECC and error handling </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience in product integration with BIOS, kernel, OS, tooling, and BMCs </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience with board and system design </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc. </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Hands-on silicon development experience <span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}"> </span></li>
</ul>
<p><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":2,"335559740":300}">Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.</span></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>
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