Fabric Modeling and Analysis Engineer for Scale Up Fabric at Astera Labs

San Jose, California, United StatesFull-timeCTO OfficePosted 2 months ago

About the Role

<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div>Fabric Modeling and Analysis Engineer- Scale Up Fabric  <span data-ccp-parastyle="First Paragraph" data-ccp-parastyle-defn="{"ObjectId":"eeed19a5-d5cb-52b4-b7a2-054cd7cfbffb|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",469775450,"First Paragraph",201340122,"2",134234082,"true",134233614,"true",469778129,"FirstParagraph",335572020,"1",335559739,"180",335559738,"180",469775498,"Body Text",469778324,"Normal"]}">Role Overview  Astera Labs is powering the connectivity behind rack-scale AI, and our Scorpio Scale-Up Fabric is central to how tomorrow’s GPU clusters scale. As a Fabric Modeling and Analysis Engineer, you will own the performance models that shape this fabric — quantifying bandwidth, latency, and throughput ceilings, and predicting how Scorpio hardware behaves under real AI/ML workloads long before silicon exists.  This is a high-impact role for an engineer who thrives where architecture, performance analysis, and software converge. Your models will shape the next generate products and enable informed architectural decisions ahead of tape-out, surface bottlenecks that only appear at scale, and translate directly into roadmap and IP decisions. As Astera Labs continues its hyper-growth, you’ll be the internal authority on fabric modeling.  Key Responsibilities  <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="1"><span data-ccp-parastyle="Compact" data-ccp-parastyle-defn="{"ObjectId":"1c404021-ed7f-59ca-94f3-e0153ac20548|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",469775450,"Compact",201340122,"2",134234082,"true",134233614,"true",469778129,"Compact",335572020,"1",335559739,"36",335559738,"36",469778324,"Normal"]}">Simulation Infrastructure & Model Correlation </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="2">Design, implement, and maintain features in AI/ML system simulators and fabric models, extending support for collective communication, transport, topology, congestion, routing, buffering, scheduling, and traffic management </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2">Improve simulator fidelity, scalability, debuggability, and runtime performance across packet-level, flow-level, and analytical backends, and build reusable abstractions and APIs for end-to-end simulation flows </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="2">Continuously calibrate and validate models against benchmark data from the Performance Engineering team, owning the correlation between model predictions and measured silicon across scale up fabric generations </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Analytical & Fabric Performance Modeling </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="2">Design and implement transaction-level or cycle-approximate system models of the Scale up fabric, enabling rigorous evaluation of new architectural ideas early in the design cycle, well before tape-out </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2">Develop and own theoretical roofline and analytical models that establish bandwidth, latency, and throughput ceilings for the Scale-Up fabric, mapping AI/ML workload demands against fabric capabilities to identify compute-bound vs. fabric-bound regimes </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="2">Model AI/ML collective communication patterns (AllReduce, AllGather, ReduceScatter) and next-generation features such as advanced congestion control, In-Network Computing, and novel resiliency at scale </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">Workload Characterization, Scalability & Topology Analysis </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="2">Model fabric performance as clusters scale from tens to thousands of GPUs, evaluating topological choices and configurations and their impact on latency, bandwidth, and congestion </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2">Proactively identify architectural bottlenecks that would otherwise only surface at scale and propose solutions in the in-house network model </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1">Innovation, Competitive Analysis & Roadmap Influence </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="8" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="2">Build analytical models of competing fabric architectures and evaluate emerging interconnect technologies — such as UALink, ESUN, and optical fabrics — to assess their impact on future Scorpio generations </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="8" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2">Translate modeling insights into architectural innovation proposals and patentable IP, and propose future switch features to architecture and engineering teams </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="8" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="2">Serve as the internal authority on fabric modeling, partnering with ASIC architects and product teams to drive roadmap and feature decisions, support early customer engagement, and produce modeling reports, white papers, and presentations for engineering, product, and executive audiences </li> </ul> Basic Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="1">Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">8+ years of relevant background in network modeling, system architecture, and scaleup fabric benchmarking and analysis </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">Strong programming skills in Python and/or C++ for building and analyzing system models </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1">Hands-on experience with cycle-approximate or event-driven system modeling and simulation </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1">Deep experience designing, enhancing, and maintaining fabric models using established frameworks such as Astera-Sim, Garnet, NS-3, ATLAHS, BookSim, or in-house simulators </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1">Solid understanding of high-speed interconnect and switching fundamentals, including the physical layer, and protocols such as PCIe (Gen 6/7), ESUN, UEC or UALink </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1">Experience characterizing performance across bandwidth, latency, buffering, and congestion in network model or cluster </li> </ul> Preferred Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="1">MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Familiarity with AI/ML collective communication (AllReduce, AllGather, ReduceScatter) and large-scale LLM training/inference traffic patterns </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">Background correlating models against emulation or silicon measurements, and analyzing competitive or emerging fabric architectures </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335551671":0,"335552541":1,"335559683":0,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1">Strong communication skills with a track record of influencing architectural decisions and contributing to IP/patents </li> </ul> Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.     <div class="content-conclusion">We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</div>

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