Principal Digital Design Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop <span data-teams="true">advanced high speed SerDes</span> wireline and optical transceivers for AI systems.&nbsp;</p> <p>Basic Qualifications:</p> <ul> <li>Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.</li> <li>5-10 years of experience in digital design for high-speed DSP data path.</li> <li>Be proficient in coding System Verilog for complex design blocks.</li> <li>Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.</li> <li>Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.</li> <li>Have experience with timing fixes, area and power optimizations, and resolving silicon issues.</li> </ul> <p>Required Experience:</p> <ul> <li>Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.</li> <li>Code and deliver high-quality RTL to the PD and DV teams.</li> <li>Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.</li> <li>Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.</li> <li>Partner with the DV team to root-cause and fix design bugs.</li> </ul> <p>Preferred Experience:</p> <ul> <li>Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes</li> <li>Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.</li> </ul> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>