Principal Digital Design Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Job Description</strong></p> <p>We are looking for <strong>Principal Digital Design Engineers </strong>with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.</p> <p><strong>Basic Qualifications:</strong></p> <ul> <li>Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.</li> <li>+8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.</li> <li>Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.</li> <li>Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!</li> <li>Authorized to work in the US and start immediately.</li> </ul> <p><strong>Required Experience:</strong></p> <ul> <li>Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.</li> <li>Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.</li> <li>Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production</li> <li>Experience with Synopsys and/or Cadence digital design tools/flows</li> <li>Good knowledge of design for test (DFT), stuck-at and transition scan test insertion</li> <li>Familiarity with UVM based design verification</li> <li>Silicon bring-up and debug expertise</li> <li>Small-geometry CMOS (≤28nm) design</li> </ul> <p><strong>Preferred Experience:</strong></p> <ul> <li>Firmware development with C-language, scripting with Python or other equivalent programming languages.</li> <li>Development/support for PCIe or Ethernet Switch products.</li> </ul> <div> <div> <p>The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.&nbsp;</p> </div> </div><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>