Senior Verification Engineer at AST SpaceMobile

Hyderabad, Telangana, IndiaFull-timeDigital SolutionsPosted 25 days ago

About the Role

<div class="content-intro">AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.</div>Position Overview  We are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in System Verilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams.   Key Responsibilities:  <ul> <li>Develop and maintain System Verilog/UVM-based verification environments for FPGA block-level and top-level designs  </li> <li>Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage  </li> <li>Perform simulation-based verification of FPGA designs using industry-standard simulators  </li> <li>Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers</li> <li>Integrate and maintain VIPs, scoreboards, checkers, and reference models  </li> <li>Support FPGA bring-up, validation, and debug activities on FPGA platforms and evaluation boards  </li> <li>Review FPGA RTL, verification code, and test plans to ensure quality and completeness  </li> <li>Mentor junior engineers and contribute to FPGA verification best practices</li> <li>Support regression runs, coverage closure, and release signoff </li> </ul> Qualifications  Education:   Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field  Experience:  4–8 years of hands-on experience in functional verification  Preferred Qualifications:   <ul> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Familiarity with cadence tools like Xcelium </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Familiarity with Xilinx Vivado </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Experience with hardware/software co-verification  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Knowledge of high-speed interfaces (AXI, AXIStream, DDR, SPI)  </li> </ul> Soft Skills:  <ul> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Strong analytical and debugging skills  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Ability to work effectively in cross-functional teams  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Excellent written and verbal communication skills  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Self-driven with the ability to own verification tasks end-to-end  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">High attention to detail and commitment to quality </li> </ul> Technology Stack:  <ul> <li>Languages: System Verilog, Verilog, VHDL (working knowledge)  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Verification Methodology: UVM  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Simulation Tools: Xcelium, Questa, VCS  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">FPGA Tools: Xilinx Vivado  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Debug Tools: SimVision  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Scripting: Python, Tcl, Shell  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Version Control: Git   </li> </ul> Physical Requirements  <ul> <li>Ability to work in a standard office environment  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1">Ability to use a computer for extended periods  </li> <li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1">Occasional lab work for FPGA bring-up and debug </li> </ul> This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. <div class="content-conclusion">AST SpaceMobile is an Equal Opportunity, at will Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.</div>

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