Senior FPGA Engineer (DV Equities) at DV Trading LLC

<p><span style="font-size: 10pt;"><strong>About Us</strong>:</span><br><span style="font-size: 10pt;">Founded 20 years ago and headquartered in Chicago, the <span data-highlighted="true" data-vc="highlighted-text"><span class="_kqswh2mm"><span class="_5pioz8co _189e1dm9 _1il9buyh _19lc184f _d0altlke" data-testid="definition-highlighter">DV</span></span></span> Group of financial services firms has grown to more than 600 people operating throughout North America, Europe and Asia. Since spinning out of a large brokerage firm in 2016, <span data-highlighted="true" data-vc="highlighted-text">DV</span> Trading has rapidly scaled as an independent proprietary trading firm utilizing its own capital, trading strategies, and risk management methodologies to provide liquidity to worldwide financial markets and hedging opportunities to commodity producers and users. Now, <span data-highlighted="true" data-vc="highlighted-text">DV</span> group affiliates include two broker dealers, a cryptocurrency market making firm, and a bourgeoning investment adviser.</span><br><br><span style="font-size: 10pt;"><strong>Role Overview:<br></strong>We are looking for an exceptional Senior FPGA Engineer to join our semi-systematic equities team. In this role, you will architect and deliver ultra-low-latency FPGA trading systems that drive our competitive edge across global equity and futures exchanges. This position offers the opportunity to lead, innovate, and push the limits of hardware performance in a fast-paced trading environment.<strong><br><br>Key Responsibilities: </strong></span></p> <p><span style="font-size: 10pt;">Technical Leadership</span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Lead and mentor a team of FPGA engineers developing next-generation hardware solutions for market making.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Architect and implement ultra-low-latency trading systems optimized for global equity and futures markets.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Define and execute the technical vision and roadmap for FPGA-based trading infrastructure.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Partner closely with quantitative researchers, software developers, and network engineers to deliver integrated, high-performance trading platforms.</span></li> </ul> <p><span style="font-size: 10pt;">System Development</span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Design and implement high-throughput FPGA firmware for market data feed handling and order execution.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Build modular, reusable, and scalable FPGA architectures supporting exchanges such as NYSE, NASDAQ and CBOE.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Develop robust testing frameworks and automated deployment pipelines to ensure stability and reliability in production.</span></li> </ul> <p><span style="font-size: 10pt;"><strong>Required Qualifications:</strong></span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">5+ years of hands-on FPGA design and development experience, ideally within high-frequency or market-making systems.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Expert-level proficiency in SystemVerilog targeting Xilinx platforms.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Deep understanding of networking and low-level protocols (10G Ethernet, multicast, MAC/PCS layers).</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Proven track record in ultra-low-latency hardware design and performance optimization.</span></li> </ul> <p><span style="font-size: 10pt;"><em>DV is not accepting unsolicited resumes from search firms. Only search firms with valid, written agreements with DV should submit resumes in response to DV’s posted positions. All resumes submitted by search firms to DV via e-mail, the Internet, personal delivery, facsimile, or any other method without a valid written agreement shall be deemed the sole property of DV, and no fee will be paid in the event the candidate is hired by DV. DV is proud to be an equal opportunity employer and committed to creating an inclusive environment for all employees.</em></span></p>