Senior STA Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>&nbsp;</p> <h1 class="PDq2pG_selectionAnchorContainer" data-section-id="l2rpfr" data-start="0" data-end="39">Senior STA Engineer – Job Description</h1> <p data-start="41" data-end="163"><strong data-start="41" data-end="54">Position:</strong> Senior STA Engineer<br data-start="74" data-end="77"><strong data-start="77" data-end="92">Experience:</strong> 6+ years<br data-start="103" data-end="106"><strong data-start="106" data-end="119">Location:</strong> Ahmedabad<br data-start="130" data-end="133"><strong data-start="133" data-end="153">Employment Type:</strong> Full-time</p> <h3 data-section-id="1gkutcd" data-start="165" data-end="180">Job Summary</h3> <p data-start="181" data-end="519">We are looking for a <strong data-start="202" data-end="225">Senior STA Engineer</strong> with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.</p> <h3 data-section-id="164ueu3" data-start="521" data-end="545">Key Responsibilities</h3> <ul data-start="546" data-end="1999"> <li data-section-id="1r7x2uk" data-start="546" data-end="642">Own <strong data-start="552" data-end="578">STA and timing signoff</strong> activities from synthesis through physical design and tape-out.</li> <li data-section-id="177s0zq" data-start="643" data-end="720">Perform <strong data-start="653" data-end="682">MCMM/MMMC timing analysis</strong> across all functional and test modes.</li> <li data-section-id="17vnu9f" data-start="721" data-end="815">Analyze and debug <strong data-start="741" data-end="814">setup, hold, recovery, removal, min/max, and clock-related violations</strong>.</li> <li data-section-id="1ai3568" data-start="816" data-end="970">Develop, review, and validate <strong data-start="848" data-end="867">SDC constraints</strong>, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.</li> <li data-section-id="bevsbq" data-start="971" data-end="1102">Perform detailed <strong data-start="990" data-end="1030">clock tree and clock timing analysis</strong>, including skew, latency, uncertainty, jitter, and clock reconvergence.</li> <li data-section-id="168a4rc" data-start="1103" data-end="1199">Drive <strong data-start="1111" data-end="1129">timing closure</strong> in collaboration with RTL, synthesis, physical design, and ECO teams.</li> <li data-section-id="fknoyd" data-start="1200" data-end="1302">Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.</li> <li data-section-id="6uo78c" data-start="1303" data-end="1426">Perform timing analysis considering <strong data-start="1341" data-end="1425">OCV/AOCV/POCV, derates, SI/crosstalk, and process-voltage-temperature variations</strong>.</li> <li data-section-id="1u8ejn" data-start="1427" data-end="1517">Review timing constraints and methodology to ensure <strong data-start="1481" data-end="1516">signoff-quality timing analysis</strong>.</li> <li data-section-id="1qzqer7" data-start="1518" data-end="1604">Support <strong data-start="1528" data-end="1543">timing ECOs</strong> and evaluate their impact across multiple corners and modes.</li> <li data-section-id="14jafit" data-start="1605" data-end="1713">Develop and maintain <strong data-start="1628" data-end="1653">Tcl/Python automation</strong> for STA analysis, report generation, and flow optimization.</li> <li data-section-id="2q7pk2" data-start="1714" data-end="1799">Debug complex timing issues and provide technical guidance to junior STA engineers.</li> <li data-section-id="1rocp64" data-start="1800" data-end="1888">Participate in methodology development, flow improvements, and timing signoff reviews.</li> <li data-section-id="1o8j8uc" data-start="1889" data-end="1999">Coordinate with cross-functional teams to ensure project milestones and <strong data-start="1963" data-end="1985">tape-out schedules</strong> are achieved.</li> </ul> <h3 data-section-id="akeeu6" data-start="2001" data-end="2030">Required Technical Skills</h3> <ul data-start="2031" data-end="2730"> <li data-section-id="1x7tdtf" data-start="2031" data-end="2099">Strong expertise in <strong data-start="2053" data-end="2098">Static Timing Analysis and timing closure</strong>.</li> <li data-section-id="1i2njrj" data-start="2100" data-end="2191">Hands-on experience with <strong data-start="2127" data-end="2165">Synopsys PrimeTime, Cadence Tempus</strong>, or equivalent STA tools.</li> <li data-section-id="1pgzu10" data-start="2192" data-end="2259">Excellent knowledge of <strong data-start="2217" data-end="2258">SDC constraints and timing exceptions</strong>.</li> <li data-section-id="1wqrvkb" data-start="2260" data-end="2353">Strong understanding of <strong data-start="2286" data-end="2352">ASIC/SoC design, synthesis, physical design, and signoff flows</strong>.</li> <li data-section-id="dp6e8d" data-start="2354" data-end="2392">Expertise in <strong data-start="2369" data-end="2391">MCMM/MMMC analysis</strong>.</li> <li data-section-id="1rs6cru" data-start="2393" data-end="2493">Good understanding of <strong data-start="2417" data-end="2492">OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing</strong>.</li> <li data-section-id="2jokkc" data-start="2494" data-end="2595">Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.</li> <li data-section-id="1eqpk46" data-start="2596" data-end="2670">Proficiency in <strong data-start="2613" data-end="2630">Tcl scripting</strong>; Python/Perl scripting is an advantage.</li> <li data-section-id="1owq8ci" data-start="2671" data-end="2730">Strong debugging, analytical, and problem-solving skills.</li> </ul> <h3 data-section-id="lodrpc" data-start="2732" data-end="2761">Senior-Level Expectations</h3> <ul data-start="2762" data-end="3260"> <li data-section-id="u8kito" data-start="2762" data-end="2833">Ability to <strong data-start="2775" data-end="2832">independently own STA for a block or full-chip design</strong>.</li> <li data-section-id="1uizkal" data-start="2834" data-end="2923">Ability to identify root causes of complex timing violations and drive them to closure.</li> <li data-section-id="37tjb2" data-start="2924" data-end="3018">Ability to interact effectively with <strong data-start="2963" data-end="3017">design, RTL, synthesis, PD, CTS, and signoff teams</strong>.</li> <li data-section-id="8p99e4" data-start="3019" data-end="3088">Experience mentoring junior engineers and reviewing their STA work.</li> <li data-section-id="7nlt1w" data-start="3089" data-end="3154">Strong ownership, communication, and project-management skills.</li> <li data-section-id="a46flu" data-start="3155" data-end="3260">Ability to work in a fast-paced semiconductor environment and deliver against tight tape-out schedules.</li> </ul> <h3 data-section-id="g9ewcs" data-start="3262" data-end="3275">Education</h3> <p data-start="3276" data-end="3374" data-is-last-node="" data-is-only-node=""><strong data-start="3276" data-end="3303">B.E./B.Tech/M.E./M.Tech</strong> in Electronics, Electrical Engineering, VLSI, or a related discipline.</p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>