Senior Software Engineer- AI for RTL Design & Formal Verification at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>&nbsp;</p> <p><span style="font-size: 10pt;"><strong><span data-olk-copy-source="MessageBody">Senior Software Engineer – AI for RTL Design &amp; Formal Verification</span></strong></span></p> <p><span style="font-size: 10pt;">Join Astera Labs' AppliedAI organization, where we're building the connectivity infrastructure that powers AI and cloud data centers. Our team sits at the intersection of&nbsp;digital and analog&nbsp;design, verification, and AI tooling, tackling the complexity of next-generation semiconductor products at the pace our industry demands. We're looking&nbsp;to develop and deploy AI-driven agents that accelerate RTL and physical design, static analysis, and formal verification workflows. The ideal candidate combines a strong ASIC and software engineering background with hands-on exposure to digital or analog design or verification, and is excited to apply LLMs and agentic systems to real chip design problems.</span></p> <p><span style="font-size: 10pt;"><strong>What You'll Be Doing</strong></span></p> <p><span style="font-size: 10pt;">Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies to support RTL, physical and analog design, static/lint checking, and formal verification flows.&nbsp;Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems that help designers and verification engineers debug faster and close coverage sooner.&nbsp;Develop agentic AI solutions for tasks such as RTL rule and lint checking, RTL optimization, &nbsp;bug triage, formal proof convergence, and static verification report analysis; fine-tune and integrate these solutions with existing CAD/EDA flows. Build and maintain design databases and dashboards that combine agentic and deterministic retrieval to surface relevant engineering data and speed up design closure.&nbsp;Collaborate closely with RTL design, DV, formal verification, and CAD/EDA teams to understand pain points and translate them into AI-assisted tooling.</span></p> <p><span style="font-size: 10pt;"><strong>Basic Qualifications</strong></span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Bachelor's, Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar) is strongly preferred.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Strong analytical, communication, and interpersonal skills, with a proven ability to work effectively in a fast-paced, cross-functional startup environment.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">A proactive, self-directed approach to problem-solving and comfort operating with ambiguity.</span></li> </ul> <p><span style="font-size: 10pt;"><strong>Ways to Stand Out</strong></span></p> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Direct experience applying AI/ML techniques to EDA or CAD flow problems.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Proficiency in modern software engineering practices, including version control, testing, and CI/CD.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">A track record of learning across disparate domains (AI/ML and hardware design) and combining them into novel engineering solutions.</span></li> </ul> <p></p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea" data-pm-slice="1 1 []">Salary range is $160,500 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p> <p></p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>