Physical Design Engineering, VP at Astera Labs

San Jose, California, United StatesFull-timeASIC EngineeringPosted 2 months ago

About the Role

<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div>Astera Labs is seeking a VP of Physical Design to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe and UALink technologies. This strategic leadership role will drive the physical implementation of highly complex, multi-die chiplet architectures that are essential to enabling rack-scale AI infrastructure. As VP, you will scale and mentor a growing team of physical design engineers while establishing the methodologies and flows required to deliver multiple high-performance tapeouts in advanced process nodes.  This role sits at the intersection of cutting-edge connectivity technology and semiconductor execution excellence. You will partner closely with architecture, digital design, packaging, and silicon engineering teams to ensure our switching solutions meet the aggressive performance, power, and area targets demanded by hyperscale AI data centers. Your expertise in interposer design, die-to-die interfaces, advanced packaging, and timing closure will be critical as Astera Labs continues to push the boundaries of AI connectivity with PCIe Gen 6/7 and UALink technologies.  Key Responsibilities  Strategic Physical Design Leadership  <ul> <li>Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity </li> <li>Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs </li> <li>Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces </li> <li>Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects </li> </ul> Team Building & Leadership  <ul> <li>Scale and develop a world-class physical design organization to support aggressive product roadmap </li> <li>Manage and mentor Directors, Managers, and senior engineers across the physical design team </li> <li>Foster a culture of technical excellence, innovation, and collaboration </li> <li>Partner with HR and recruiting to attract top physical design talent </li> </ul> Cross-Functional Collaboration & Execution  <ul> <li>Partner with architecture and digital design teams to influence RTL for physical implementation success </li> <li>Collaborate with packaging engineering on advanced 2.5D/3D integration strategies and interposer design </li> <li>Work closely with silicon engineering and DFT teams to ensure robust designs through tapeout and bring-up </li> <li>Drive resolution of critical timing, power, and signal integrity challenges in high-speed SerDes and switching fabrics </li> </ul> Basic Qualifications  <ul> <li>Bachelor's degree in Electrical Engineering, Computer Engineering, or related field </li> <li>15+ years of experience in physical design and implementation of complex SoCs or ASICs </li> <li>Proven track record leading physical design teams and delivering multiple successful tapeouts in advanced process nodes (7nm or below) </li> <li>Deep expertise in chiplet architectures, interposer design, and die-to-die interface implementation </li> <li>Strong understanding of advanced packaging technologies including 2.5D and 3D integration </li> <li>Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies </li> <li>Experience managing and scaling engineering teams of 20+ people </li> </ul> Preferred Qualifications  <ul> <li>Master's degree or PhD in Electrical Engineering or related field </li> <li>Experience with UCIe, PCIe Gen 6/7, or other high-speed SerDes physical implementation </li> <li>Background in AI/ML infrastructure, networking ASICs, or high-performance switching products </li> <li>Deep expertise with Cadence and/or Synopsys physical design tools and flows </li> <li>Experience with advanced DFT integration and design for manufacturability (DFM) </li> <li>Track record of innovation in physical design methodologies and automation </li> <li>Strong leadership and communication skills with ability to influence across organizations </li> </ul> Salary range is $250,600 to $375,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. <div class="content-conclusion">We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</div>

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