Tech Lead, Digital Design Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>&nbsp;</p> <p class="p8i6j01 paragraph"></p> <h2 class="wnfdntj _1ibi0s35e _1ibi0s36a" data-pm-slice="1 1 []">Role Overview</h2> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.</p> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams. You will help advance scalable fabric solutions built around UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet as Astera Labs continues to deliver purpose-built connectivity for demanding AI workloads.</p> <h2 class="wnfdntj _1ibi0s35e _1ibi0s36a">Key Responsibilities</h2> <ul class="wnfdntg"> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Digital Architecture and RTL Design</strong></p> <ul class="wnfdntg"> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Develop front-end design solutions for high-performance networking and server connectivity applications.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.</p> </li> </ul> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Design Implementation and Signoff</strong></p> <ul class="wnfdntg"> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.</p> </li> </ul> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Verification, Bring-Up, and Technical Leadership</strong></p> <ul class="wnfdntg"> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.</p> </li> </ul> </li> </ul> <h2 class="wnfdntj _1ibi0s35e _1ibi0s36a">Basic Qualifications</h2> <ul class="wnfdntg"> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Bachelor’s degree in Electrical Engineering or a related field.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Authorized to work in the United States.</p> </li> </ul> <h2 class="wnfdntj _1ibi0s35e _1ibi0s36a">Preferred Qualifications</h2> <ul class="wnfdntg"> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Master’s degree in Electrical Engineering or a related field.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Experience developing or supporting PCIe or Ethernet switch products.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with UVM-based design verification and coverage-driven debug.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.</p> </li> <li class="wnfdntf _1ibi0s35c"> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.</p> </li> </ul> <p class="wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Salary range is $175,500 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p> <p class="p8i6j01 paragraph"></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>