Lead Logic Design Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Lead Logic Design Engineer&nbsp;</strong></p> <p><strong>Experience</strong></p> <p><strong>6-10 years</strong></p> <p><strong>Job Summary</strong></p> <p>We are seeking a Lead <strong>Logic Design Engineer</strong> with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>Lead RTL/microarchitecture development for <strong>complex connectivity IP/subsystems</strong>.</li> <li>Translate specifications and system requirements into robust hardware architecture.</li> <li>Design high-performance and scalable logic for controllers/subsystems.</li> <li>Work across connectivity IP / subsystem layers including <strong>Transaction, Data Link, and Physical interface integration</strong> as applicable to the role.</li> <li>Develop and review RTL using <strong>SystemVerilog/Verilog</strong>.</li> <li>Develop robust mechanisms for <strong>flow control, ordering, buffering, arbitration, error handling, and reliability</strong>.</li> <li>Drive performance, latency, area, and power optimization.</li> <li>Collaborate with verification teams to develop verification strategies and debug complex failures.</li> <li>Work with SoC integration and physical design teams to ensure successful implementation.</li> <li>Lead technical reviews and mentor senior engineers.</li> <li>Support post-silicon debug and root-cause analysis.</li> </ul> <p><strong>Required Skills</strong></p> <ul> <li>Extensive experience in <strong>complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe</strong>.</li> <li>Strong RTL design experience using <strong>SystemVerilog/Verilog</strong>.</li> <li>Deep knowledge of PCIe architecture and protocol.</li> <li>Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.</li> <li>Experience with simulation, lint, CDC, synthesis, and timing considerations.</li> <li>Strong debugging and problem-solving skills.</li> </ul> <p><strong>Preferred</strong></p> <ul> <li>Experience of working in switching silicon.</li> <li>Experience of working on entire cycle from concept to silicon production.</li> </ul><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>