Principal Electrical Engineer – Smart Cable Modules at Astera Labs

Shanghai Shi, ChinaFull-timeHardware EngineeringPosted 20 days ago

About the Role

<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div>We are looking for a Principal Electrical Engineer to take strategic ownership of our Smart Cable Module (SCM) hardware platform. This is a senior individual-contributor role that combines deep technical leadership with cross-organizational influence - you will define the electrical architecture of our next-generation active copper cable assemblies and pluggable modules in OSFP, QSFP-DD, and emerging form-factor enclosures targeting 400G, 800G, and beyond.  As a Principal Engineer you will set design direction, establish engineering standards, and serve as the primary technical authority on module hardware across the full product lifecycle - from concept and architecture through production release and sustaining engineering. You will partner with cross functional team, contract manufacturers, firmware teams, and hyperscale customers to deliver differentiated, high-reliability products for data center AI/ML fabric and high-performance computing applications.    Key Responsibilities  Architecture & Technical Leadership  <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Define and own the end-to-end electrical architecture for smart cable modules, including SerDes channel topology, power delivery strategy, and thermal budgeting for muti-Gig (112G PAM4 and 56G NRZ ) designs </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Establish and maintain internal electrical design standards, PCB layout rules, and SI/PI guidelines that the broader hardware team  </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Lead technical reviews (architecture, schematic, layout, DVT) and provide authoritative sign-off on high-speed digital designs </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Contribute to the module hardware roadmap in alignment with host ASIC platform generations, MSA form-factor evolution, and customer requirements </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Evaluate and select components; engage directly with supplier engineering teams on reference design adaptation and silicon bring-up support </li> </ul>   Electrical Design Ownership  <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Drive schematic capture and PCB design for complex multi-layer modules housing muti-Gig SerDes retimer or DSP ASICs in thermally and spatially constrained OSFP/QSFP-DD enclosures </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Own power delivery design including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes. </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Review and recommendation on PCB stack-up, impedance targets, via structures, and differential-pair routing rules; review and approve layout execution with sufficient SI understanding to ensure first-pass compliance </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Define module management hardware architecture: I2C topology, register map implementation, microcontroller selection, and diagnostic monitoring interface circuitry </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Perform analog and mixed-signal sub-circuit design including clock distribution, oscillator selection, ESD protection, and supervisory logic </li> </ul>   Validation & Bring-Up Leadership  <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1">Author/co-author hardware bring-up strategies, debug plans, and acceptance test procedures for new module designs; lead or directly execute board bring-up. </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="12" data-aria-level="1">Oversee firmware integration testing, control-interface validation, and module diagnostic monitoring verification </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1">Lead root-cause analysis on complex hardware failures; review failure analysis reports and implement changes. </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1">Define and champion DFT/DFM strategies with CM and PCB fabrication partners to improve yield and reduce manufacturing cost </li> </ul>   Cross-Functional & Organizational Impact  <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="15" data-aria-level="1">Collaborate with firmware and software teams to define initialization sequences, power management schemes, and real-time diagnostic algorithms </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="16" data-aria-level="1">Represent the organization in relevant MSA, and IEEE standards working groups; influence specification development in support of company product strategy </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="17" data-aria-level="1">Mentor and technically develop senior and mid-level engineers; elevate the hardware team's collective capabilities in high-speed design </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="18" data-aria-level="1">Contribute to strategic hiring, technical onboarding, and department-level engineering process improvement </li> </ul>   Required Qualifications  <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="19" data-aria-level="1">Bachelor’s or Master’s degree in electrical engineering or closely related field;  </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="20" data-aria-level="1">10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="21" data-aria-level="1">Demonstrated track record of architecting and delivering production hardware with 56G / 112G and faster SerDes interfaces (Ethernet, PCIe, or InfiniBand) </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="22" data-aria-level="1">Expert-level understanding of signal integrity principles - impedance control, differential pair management, eye mask budgeting, channel loss allocation - sufficient to author design rules and review layout without performing full SI simulation </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="23" data-aria-level="1">Proficiency with EDA tools: industry-standard schematic capture (Cadence Allegro / OrCAD) and PCB layout review </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="24" data-aria-level="1">Deep familiarity with OSFP, QSFP-DD800, and SFP-DD MSA mechanical, electrical, and management specifications </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="25" data-aria-level="1">Hands-on experience with CMIS 5.x / SFF-8636 module management and I2C/MDIO interface design </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="26" data-aria-level="1">Proven ability to lead hardware bring-up and debug complex mixed-signal failures using high-bandwidth oscilloscopes and protocol analyzers </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="27" data-aria-level="1">Strong PDN design fundamentals: multi-rail sequencing, transient response, decoupling strategy, and thermal-electrical co-analysis </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="28" data-aria-level="1">Experience interfacing with silicon vendors/teams on customizing reference design, silicon errata management, and platform bring-up </li> </ul>   Preferred Qualifications  <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="29" data-aria-level="1">Experience at the architecture or lead engineer level on 800G or beyond module programs </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="30" data-aria-level="1">Familiarity with co-packaged optics (CPO) or linear drive (LPO) module electrical architecture </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="31" data-aria-level="1">Working knowledge of host-side switching ASIC electrical interfaces and SerDes equalization schemes </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="32" data-aria-level="1">Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="33" data-aria-level="1">Experience with PCIe Gen 5/6 retimer module designs </li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":640,"335559991":320,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="34" data-aria-level="1">Scripting fluency in Python for lab automation, measurement data reduction, or hardware characterization workflows </li> </ul><div class="content-conclusion">We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</div>

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