Principal Engineering Program Manager (EPM) at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>&nbsp;</p> <h1 class="wnfdnti _1ibi0s33y _1ibi0s34u" data-pm-slice="1 1 []">Principal Engineering Program Manager, (EPM)</h1> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Location:</strong> San Jose, CA (Onsite)</p> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Role Overview</h2> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">As a Principal Engineering Program Manager on our Analog/Mixed-Signal (AMS) team, you will drive the execution of the complex silicon programs that power Astera Labs' purpose-built connectivity solutions. You'll orchestrate multi-disciplinary teams — spanning circuit design, layout, verification, and silicon validation — to deliver high-performance AMS IP on schedule, on budget, and to spec.</p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This is a high-impact leadership role at a hyper-growth company defining the connectivity backbone of the AI era. You'll own program plans from concept through tape-out and silicon bring-up, surface and resolve cross-functional risks, and bring the operational rigor that turns ambitious engineering into products shipping at rack scale. Your ability to align stakeholders and keep fast-moving programs on track will be central to Astera's continued momentum.</p> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Key Responsibilities</h2> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Program Planning &amp; Execution</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Define, drive, and maintain end-to-end program schedules for AMS IP development, from specification through tape-out and validation</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Manage critical path, milestones, and dependencies across circuit design, layout, verification, and silicon bring-up</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Establish and track program metrics, budgets, and deliverables to ensure predictable, high-quality outcomes</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Cross-Functional Leadership</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Partner with AMS design, digital, systems, product, and operations teams to align priorities and resolve blockers</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Lead program reviews, drive decision-making, and communicate status, risks, and trade-offs to leadership and stakeholders</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Coordinate with external partners, foundries, and vendors on tape-out readiness and schedule commitments</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Risk Management &amp; Process Excellence</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Proactively identify, quantify, and mitigate technical and schedule risks across concurrent programs</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Drive continuous improvement of program management processes, tools, and best practices for AMS execution</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Champion clear documentation, accountability, and operational discipline across the program lifecycle</p> </li> </ul> </li> </ul> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Basic Qualifications</h2> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">8+ years of experience in program or project management within semiconductor, IC, or hardware development</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Proven track record managing complex silicon or AMS/IP programs through tape-out and silicon validation</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Strong understanding of the ASIC/IC development lifecycle, including design, verification, layout, and bring-up</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Excellent stakeholder management, communication, and cross-functional leadership skills</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Proficiency with program management and collaboration tools (e.g., Microsoft Project, Microsoft 365)</p> </li> </ul> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Preferred Qualifications</h2> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">MS in Electrical Engineering, Computer Engineering, or a related field</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Direct experience with analog/mixed-signal or high-speed connectivity programs</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">PMP certification or equivalent program management credential</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Familiarity with foundry engagement, tape-out flows, and vendor/IP coordination</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Ability to thrive and lead through ambiguity in a fast-paced, hyper-growth environment</p> </li> </ul> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p> <p class="p8i6j01 paragraph">&nbsp;</p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>