FPGA Firmware Engineer at ALTEN Technology USA

<div class="content-intro"><p>We’re ALTEN Technology USA, an engineering company helping clients bring groundbreaking ideas to life—from advancing space exploration and life-saving medical devices to building autonomous electric vehicles. With 3,000+ experts across North America, we partner with leading companies in aerospace, medical devices, robotics, automotive, commercial vehicles, EVs, rail, and more.</p> <p>As part of the global ALTEN Group—57,000+ engineers in 30 countries—we deliver across the entire product development cycle, from consulting to full project outsourcing.</p> <p>When you join ALTEN Technology USA, you’ll collaborate on some of the world’s toughest engineering challenges, supported by mentorship, career growth opportunities, and comprehensive benefits. We take pride in fostering a culture where employees feel valued, supported, and inspired to grow.</p></div><p><em><span style="text-decoration: underline;"><strong></strong></span></em></p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">Role Overview</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;"><span style="text-decoration: underline;"><em><strong>This is a fully REMOTE role</strong></em></span></p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">You will be a key contributor to a safety-critical embedded systems engineering team, responsible for the design, implementation, and verification of preliminary FPGA logic for overspeed protection and ARINC 429 communication systems. Working from defined system requirements and architecture provided by the systems engineering team, you will develop and simulate firmware in a structured, DO-254-aligned development environment using Microchip's Libero toolchain.</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">Key Responsibilities</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <ul style=" margin-top: 0in; margin-bottom: 0in;" type="disc"> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Design and verify preliminary FPGA logic for overspeed protection functions, implementing requirements in firmware based on system engineer-supplied architecture and specifications</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Design and verify preliminary FPGA logic for ARINC 429 communication, leveraging existing design where applicable and extending functionality per updated requirements</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Develop and execute simulation-based verification plans to validate functional correctness of all FPGA logic prior to hardware integration</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Validate all digital inputs and outputs with particular attention to the microprocessor interface on both overspeed and communication FPGAs</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Provide complete pin allocation documentation for both FPGA designs in support of hardware team integration</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Collaborate with systems engineers to interpret preliminary requirements and translate them into implementable firmware logic</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Participate in design reviews, verification reviews, and technical documentation as required by the program schedule</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Support FPGA family and device sizing selection in coordination with the systems and hardware teams</span></li> </ul> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">Development Environment</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <ul style=" margin-top: 0in; margin-bottom: 0in;" type="disc"> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">EDA Tool: Libero SoC (Microchip Technology)</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">HDL: VHDL or Verilog</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Simulation: ModelSim (Microsemi edition) integrated within Libero</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">FPGA Platform: Microchip (family and device size to be determined)</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Workstation: Provided on-site</span></li> </ul> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">Required Qualifications</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <ul style=" margin-top: 0in; margin-bottom: 0in;" type="disc"> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">4+ years of experience in FPGA firmware design and verification for embedded or avionics applications</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Proficiency in VHDL or Verilog and RTL design methodology</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Experience with Microchip/Microsemi Libero SoC toolchain, or demonstrated experience with equivalent FPGA EDA tools (Vivado, Quartus) with ability to transition</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Familiarity with ARINC 429 protocol including transmit/receive channel architecture, word structure, and timing requirements</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Understanding of digital I/O interfacing, microprocessor bus interfaces, and pin allocation methodology</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Experience developing and executing simulation-based verification using ModelSim or equivalent</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Ability to work from system-level requirements and architecture documents to implement firmware logic independently</span></li> </ul> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">Nice to Have</p> <p style="margin: 0in; font-family: Calibri; font-size: 11.0pt;">&nbsp;</p> <ul style=" margin-top: 0in; margin-bottom: 0in;" type="disc"> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Experience with DO-254 design assurance processes for airborne electronic hardware</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Familiarity with overspeed protection logic or other safety-critical FPGA functions in aerospace or defense applications</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Experience with existing ARINC 429 IP cores and integration into custom FPGA designs</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Static timing analysis using SmartTime or equivalent tools</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Background in requirements traceability and configuration management in a regulated development environment</span></li> <li style="margin-top: 0; margin-bottom: 0; vertical-align: middle;"><span style="font-family: Calibri; font-size: 11.0pt;">Knowledge of Microchip PolarFire or SmartFusion2 device families</span></li> </ul> <p><em><span style="text-decoration: underline;"><strong></strong></span></em></p> <p><strong><span data-contrast="none">Salary Range: $135,000-$140,000/K</span></strong></p> <p><span data-contrast="auto">The actual salary offered is dependent on various factors including, but not limited to, location, the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559738&quot;:100,&quot;335559739&quot;:100,&quot;335559740&quot;:240}">&nbsp;</span></p><div class="content-conclusion"><p>ALTEN Technology is an Equal Opportunity Employer. Our Policy is to extend opportunities to qualified applicants and employees on an equal basis regardless of an individual’s age, race, color, sex, religion, national origin, disability, sexual orientation, gender identity/expression or veteran status.</p> <p><em><strong>Please beware of job seeker scams and see this <a href="https://www.alten.com/careers/job-offers/">important notice</a> on our careers page for more information about our recruiting process.</strong></em></p> <p><strong>Compliance Notice: </strong>Alten USA is a federal contractor subject to the requirements of the Vietnam Era Veterans’ Readjustment Assistance Act (VEVRAA) and Executive Order 11246. We are an Equal Opportunity Employer and consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.</p> <p><strong>Drug Screening Requirement: </strong>As a federal contractor, Alten USA maintains a drug-free workplace. All candidates selected for employment will be required to successfully complete a pre-employment drug screening as a condition of hire.</p></div>