Principal Logic Design Engineer - UALink IP/Subsystem at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Principal Logic Design Engineer – UALink IP/Subsystem</strong></p> <p><strong>Experience</strong></p> <p><strong>10–15 years</strong></p> <p><strong>Job Summary</strong></p> <p>We are looking for a <strong>Principal Logic Design Engineer</strong> with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for <strong>UALink-based IP/subsystems</strong>.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>Lead architecture and RTL development for UALink IP/subsystems.</li> <li>Translate protocol and system requirements into scalable hardware architecture.</li> <li>Design high-bandwidth, low-latency data paths and control logic.</li> <li>Develop robust mechanisms for <strong>flow control, ordering, buffering, arbitration, error handling, and reliability</strong>.</li> <li>Define interfaces between UALink and other SoC/interconnect components.</li> <li>Develop and review SystemVerilog RTL.</li> <li>Drive design optimization for performance, power, area, and latency.</li> <li>Work closely with verification, physical design, SoC integration, and firmware teams.</li> <li>Review design specifications and contribute to architectural decisions.</li> <li>Debug complex simulation and integration issues.</li> <li>Provide technical leadership and mentorship.</li> </ul> <p><strong>Required Skills</strong></p> <ul> <li>Strong experience in <strong>RTL and microarchitecture development</strong>.</li> <li>Experience with high-speed interconnects and/or coherent fabrics.</li> <li>Strong understanding of computer architecture, networking/interconnect concepts, and data movement.</li> <li>Proficiency in SystemVerilog/Verilog.</li> <li>Strong understanding of CDC, reset architecture, performance, and hardware design methodology.</li> </ul> <p><strong>Preferred</strong></p> <ul> <li>Direct <strong>UALink</strong> experience.</li> <li>Experience with <strong>PCIe, CXL, CCIX, CHI, Ethernet</strong>, or similar protocols.</li> <li>Experience in AI/accelerator or high-performance compute systems.</li> </ul><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>