Senior Principal Electrical Engineer at CHAOS Industries
Hawthorne, California, United StatesFull-timeEngineering Posted about 1 month ago
Apply with PipelineAbout the Role
<p>CHAOS Industries is redefining modern defense with a multi-product portfolio that gives the ultimate advantage—domain dominance. The company's products are powered by Coherent Distributed Networks (CDN™), empowering warfighters, commercial air operators, and border protection teams to act faster, adapt rapidly, and stay ahead of evolving threats. </p>
<p>CHAOS Industries was founded in 2022 and has raised a total of $1 billion in funding from leading investors, including 8VC, Accel, and Valor Equity Partners. The company is headquartered in Los Angeles, with offices in Washington, D.C., San Francisco, San Diego, Seattle, and London. For more information, please visit <a href="https://www.chaosinc.com">www.chaosinc.com</a>.</p>
<p><strong><span data-contrast="auto">Role Overview:</span></strong><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<p><span data-contrast="auto">CHAOS is seeking a Sr. Principal Electrical Engineer with expertise in digital circuit design and signal integrity analysis to serve as a technical authority for high-reliability digital electronics used in aerospace and military applications. This role spans the full product lifecycle, from early architecture and requirements shaping through detailed design, analysis, verification, production support, and fielded system sustainment.</span><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<p><span data-contrast="auto">The ideal candidate is a senior digital hardware technical authority with deep high-speed board design, signal integrity, and power integrity expertise; a track record of setting design direction across programs; and the ability to guide cross-disciplinary teams through ambiguous, high-consequence hardware challenges.</span><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<p><span data-contrast="auto">This is a full-time, on-site position in Hawthorne, CA.</span><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<p> <br><strong><span data-contrast="auto">Responsibilities:</span></strong><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Act as a technical authority for high-speed digital circuit design, signal integrity, and power integrity across multiple programs or product lines</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Lead design and review of complex PCBAs involving FPGAs, processors, memory devices, data converters, clocks, high-speed serial interfaces, and mixed-signal boundaries</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Lead digital hardware architecture trades and define design approaches that satisfy system performance, schedule, manufacturability, reliability, and qualification requirements</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Set standards, procedures, and review practices for digital board design, stack-up definition, layout constraints, SI/PI analysis, bring-up, and verification</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Resolve complex cross-disciplinary technical issues involving digital hardware, FPGA/software interfaces, RF coexistence, power distribution, EMI/EMC, thermal behavior, and mechanical packaging</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Guide PCB layout strategy for controlled impedance, length matching, return paths, grounding, shielding, decoupling, power distribution networks, and isolation of sensitive circuits</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Serve as the senior technical interface with customers, vendors, suppliers, and internal program leadership for digital hardware topics</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto">Mentor engineers and coordinate technical activities across digital, FPGA, embedded software, RF, power, mechanical, manufacturing, and test teams</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1"><span data-contrast="auto">Serve as technical authority for hardware integration, verification, qualification testing, production transition, failure analysis, and field support</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<p><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></p>
<p><strong><span data-contrast="auto">Minimum Requirements:</span></strong><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Bachelor's degree in Electrical Engineering with 15+ years of relevant engineering experience</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Demonstrated technical leadership of complex high-speed digital hardware</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Strong understanding of digital design fundamentals, including timing, clocking, controlled impedance, signal integrity, power integrity, grounding, decoupling, and return-path management</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Extensive experience with digital board design involving FPGAs, processors, memory devices, high-speed data converters, and board-level communication interfaces</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Experience setting PCB layout strategy and design review criteria for high-speed digital, mixed-signal, and high-reliability electronics</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Hands-on experience leading board bring-up, system integration, troubleshooting, verification, qualification, production transition, and failure analysis activities</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Demonstrated ability to set technical direction and lead engineers through ambiguous, cross-disciplinary hardware challenges</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto">Ability to obtain and maintain a U.S. security clearance</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<p><span data-ccp-props="{"201341983":0,"335559685":1080,"335559739":120,"335559740":240}"> </span></p>
<p><strong><span data-contrast="auto">Preferred Requirements:</span></strong><span data-ccp-props="{"201341983":0,"335559685":360,"335559739":120,"335559740":240}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Advanced Degree (MS or PhD) in Electrical Engineering, Systems Engineering, Physics, Mathematics or related discipline</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Experience with Avionics platforms</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Experience using Altium Designer</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Expertise with signal integrity and/or power integrity analysis tools such as HyperLynx, Sigrity, ADS, Ansys SIwave, or equivalent</span><span data-ccp-props="{"201341983":0,"335557856":16777215,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Experience with DDR, PCIe, Ethernet, JESD204, SERDES, LVDS, or similar high-speed interfaces in high-reliability systems</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Familiarity with EMI/EMC mitigation techniques and aerospace standards such as RTCA/DO-160, MIL-STD-461, MIL-STD-810, and MIL-STD-1275</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Experience establishing design standards, analysis templates, qualification approaches, or review processes for engineering teams</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto">Experience designing for manufacturability and leading transition from prototype hardware to production</span><span data-ccp-props="{"201341983":0,"335559739":120,"335559740":240}"> </span></li>
</ul>
<p><strong><br>Why CHAOS?</strong></p>
<ul>
<li><strong>Health Benefits: </strong>Medical, dental, and vision benefits 100% paid for by the company</li>
<li><strong>Additional benefits</strong>: 401k (+ 50% company match up to 6% of pay), FSA, HSA, life insurance, and more</li>
<li><strong>Our Perks: </strong>Free daily lunch, ‘No meeting Fridays’, unlimited PTO, casual dress code</li>
<li><strong>Compensation Components:</strong> Competitive base salaries, generous pre-IPO stock option grants, relocation assistance, and (coming soon!) annual bonuses</li>
<li><strong>Team Growth: </strong>250 employees and counting across 5 global offices</li>
</ul>
<div><em><strong>$190k-260k</strong></em></div>
<p><em>The stated compensation range reflects only the targeted base compensation range and excludes additional earnings such as bonus, equity, and benefits. If your compensation requirements fall outside of the range, we still encourage you to apply. The salary range for this role is an estimate based on a range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. </em></p>
<p> </p>
<hr>
<h3>Recruiting Agencies: CHAOS Industries does not accept unsolicited resumes or outreach. Unsolicited submissions will not be reviewed or compensated.</h3>
<hr>
<p> </p>
<p><em>#LI-onsite</em></p>
Related Roles
Software Engineer, Applied AI
CHAOS Industries
San Francisco, California, United StatesSenior Embedded Software Engineer
CHAOS Industries
San Diego, California, United StatesDirector of Supply Chain
CHAOS Industries
Hawthorne, California, United StatesSenior Network Administrator
CHAOS Industries
Hawthorne, California, United StatesSenior Test Automation Software Engineer
CHAOS Industries
Hawthorne, California, United StatesForward Deployed Engineer - Software
CHAOS Industries
Hawthorne, California, United States