Digital Design Engineer at MKS2 Technologies

<div class="content-intro"><p>MKS2 Technologies, LLC, an award-winning high growth small business, creates innovative and customer-centric technology solutions in the areas of Cyber Security, Instructional Design and Training, Software Engineering and IT Support Services to improve the security and well-being of our clients. Our commitment to excellence and our “Mission First” orientation has resulted in steady growth and an expanding client base across government agencies. We have employees nationwide and for the past three consecutive years were named one of the fastest growing Veteran-owned companies in the nation. Please take a moment to browse through our website and learn more about what it means to serve with MKS2.</p> <hr> <p>&nbsp;</p></div><p data-start="138" data-end="193"><strong data-start="138" data-end="193">Digital Design Engineer – Secret Clearance Required</strong></p> <p data-start="195" data-end="435">Location: Tucson, AZ (On-site)<br>Job Type: W-2 Contract or Contract to hire&nbsp;<br>Clearance: Active U.S. Security Clearance required prior to start<br>Pay: $90,000 - $100,000 with full Government benefits</p> <p data-start="195" data-end="435">&nbsp;</p> <p data-start="195" data-end="435"></p> <p data-start="219" data-end="403">The Effector Digital Products department is seeking an <strong data-start="274" data-end="297">Electrical Engineer</strong> with strong <strong data-start="310" data-end="353">digital electronics design and analysis</strong> experience to support missile system development.</p> <p data-start="405" data-end="636">This role focuses on designing <strong data-start="436" data-end="467">high-speed digital circuits</strong> for applications such as <strong data-start="493" data-end="562">missile guidance, video processing, and digital signal processing</strong>, leveraging technologies like FPGAs, processors, and advanced interfaces.</p> <p data-start="638" data-end="745">You will work in a <strong data-start="657" data-end="698">collaborative engineering environment</strong>, contributing to cutting-edge defense systems.</p> <hr data-start="747" data-end="750"> <h2 data-section-id="1jfyiux" data-start="752" data-end="775"><span><strong data-start="755" data-end="775">What You Will Do</strong></span></h2> <ul data-start="777" data-end="1283"> <li data-section-id="qxvwyg" data-start="777" data-end="893">Design, analyze, simulate, test, and integrate <strong data-start="826" data-end="891">digital electronic modules and circuit card assemblies (CCAs)</strong></li> <li data-section-id="gh6dtg" data-start="894" data-end="984">Develop hardware designs involving: <ul data-start="934" data-end="984"> <li data-section-id="1y8fl2l" data-start="934" data-end="948">Processors</li> <li data-section-id="5flr1n" data-start="951" data-end="960">FPGAs</li> <li data-section-id="12mrec5" data-start="963" data-end="984">Memory components</li> </ul> </li> <li data-section-id="ir0ifx" data-start="985" data-end="1081">Work with industry-standard interfaces such as: <ul data-start="1037" data-end="1081"> <li data-section-id="3vbbp3" data-start="1037" data-end="1045">PCIe</li> <li data-section-id="1bxp9uh" data-start="1048" data-end="1060">Ethernet</li> <li data-section-id="iq04dk" data-start="1063" data-end="1081">I2C, SPI, UART</li> </ul> </li> <li data-section-id="1mrw1zf" data-start="1082" data-end="1222">Support full lifecycle development from: <ul data-start="1127" data-end="1222"> <li data-section-id="ey297z" data-start="1127" data-end="1155">Concept and requirements</li> <li data-section-id="1ei1bk4" data-start="1158" data-end="1177">Hardware design</li> <li data-section-id="1eajgdu" data-start="1180" data-end="1222">Verification, integration, and testing</li> </ul> </li> <li data-section-id="h2sznv" data-start="1223" data-end="1283">Collaborate within a multi-disciplinary engineering team</li> </ul> <hr data-start="1285" data-end="1288"> <h2 data-section-id="1nahkjd" data-start="1290" data-end="1328"><span><strong data-start="1293" data-end="1328">Core Technologies / Focus Areas</strong></span></h2> <ul data-start="1330" data-end="1560"> <li data-section-id="rtagp3" data-start="1330" data-end="1364">High-speed digital electronics</li> <li data-section-id="a9cjs8" data-start="1365" data-end="1403">FPGA and configurable logic design</li> <li data-section-id="sc2jub" data-start="1404" data-end="1474">Multi-processor system architectures (homogeneous / heterogeneous)</li> <li data-section-id="1mwxmuw" data-start="1475" data-end="1510">PCB design and simulation tools</li> <li data-section-id="3dmp3k" data-start="1511" data-end="1560">Signal integrity and power integrity analysis</li> </ul> <hr data-start="1562" data-end="1565"> <h2 data-section-id="exfopp" data-start="1567" data-end="1599"><span><strong data-start="1570" data-end="1599">Qualifications – Required</strong></span></h2> <ul data-start="1601" data-end="2256"> <li data-section-id="1fg2idk" data-start="1601" data-end="1720">Bachelor’s Degree in: <ul data-start="1627" data-end="1720"> <li data-section-id="cd4ghr" data-start="1627" data-end="1653">Electrical Engineering</li> <li data-section-id="gvgr7a" data-start="1656" data-end="1680">Computer Engineering</li> <li data-section-id="19jqndl" data-start="1683" data-end="1720">Electrical Engineering Technology</li> </ul> </li> <li data-section-id="cdqu40" data-start="1721" data-end="2024">Minimum <strong data-start="1731" data-end="1780">5+ years of digital circuit design experience</strong>, including at least two of the following: <ul data-start="1825" data-end="2024"> <li data-section-id="1n1qnhv" data-start="1825" data-end="1870">Electronic circuit design and development</li> <li data-section-id="ga2h7g" data-start="1873" data-end="1945">Full lifecycle hardware design (concept through integration/testing)</li> <li data-section-id="1y17vnc" data-start="1948" data-end="2024">PCB design process including schematic capture, analysis, and simulation</li> </ul> </li> <li data-section-id="183v6kp" data-start="2025" data-end="2098">Experience designing hardware with: <ul data-start="2065" data-end="2098"> <li data-section-id="1bhvq90" data-start="2065" data-end="2098">Processors, FPGAs, and memory</li> </ul> </li> <li data-section-id="ggo7mo" data-start="2099" data-end="2161">Active <strong data-start="2108" data-end="2159">U.S. security clearance required prior to start</strong></li> <li data-section-id="dyxtk3" data-start="2162" data-end="2191">U.S. Citizenship required</li> <li data-section-id="33uoh8" data-start="2192" data-end="2256">Ability to obtain <strong data-start="2212" data-end="2244">Special Access Program (SAP)</strong> clearance</li> </ul> <hr data-start="2258" data-end="2261"> <h2 data-section-id="1wqigrm" data-start="2263" data-end="2294"><span><strong data-start="2266" data-end="2294">Preferred Qualifications</strong></span></h2> <ul data-start="2296" data-end="3167"> <li data-section-id="1sns48q" data-start="2296" data-end="2341">Master’s Degree in Electrical Engineering</li> <li data-section-id="nlbq11" data-start="2342" data-end="2476">Experience with: <ul data-start="2363" data-end="2476"> <li data-section-id="1jxhelb" data-start="2363" data-end="2391">Embedded test techniques</li> <li data-section-id="24g1y8" data-start="2394" data-end="2419">Design for test (DFT)</li> <li data-section-id="1kw4786" data-start="2422" data-end="2448">Design margin analysis</li> <li data-section-id="4set8i" data-start="2451" data-end="2476">Design for production</li> </ul> </li> <li data-section-id="whc99s" data-start="2477" data-end="2721">Experience with tools such as: <ul data-start="2512" data-end="2721"> <li data-section-id="fwurak" data-start="2512" data-end="2575">Mentor Graphics / Siemens EDA (DxDesigner, xDX Designer VX)</li> <li data-section-id="yr9jdb" data-start="2578" data-end="2627">Xilinx tools (Vivado, Zynq Ultrascale, Artix)</li> <li data-section-id="1rsj280" data-start="2630" data-end="2687">HyperLynx (signal/power integrity, analog simulation)</li> <li data-section-id="1hdcucp" data-start="2690" data-end="2721">Xpedition Enterprise (xPCB)</li> </ul> </li> <li data-section-id="xqojwo" data-start="2722" data-end="2784">Experience designing <strong data-start="2745" data-end="2782">complex CCAs (16–32 layer boards)</strong></li> <li data-section-id="1dsvwrl" data-start="2785" data-end="2835">Experience with Constraint Editor System (CES)</li> <li data-section-id="1lyifnq" data-start="2836" data-end="2885">Knowledge of software and/or FPGA development</li> <li data-section-id="3ndsv7" data-start="2886" data-end="2958">Experience transitioning programs from <strong data-start="2927" data-end="2956">development to production</strong></li> <li data-section-id="y493z7" data-start="2959" data-end="3087">Ability to manage: <ul data-start="2982" data-end="3087"> <li data-section-id="1ebix39" data-start="2982" data-end="3014">Technical and schedule risks</li> <li data-section-id="1lu7yw5" data-start="3017" data-end="3049">Cost reduction opportunities</li> <li data-section-id="5cmmh2" data-start="3052" data-end="3087">Program timelines and resources</li> </ul> </li> <li data-section-id="dxpygm" data-start="3088" data-end="3167">Experience working in <strong data-start="3112" data-end="3165">multi-disciplinary teams across multiple projects</strong></li> </ul> <p data-start="195" data-end="435"></p><div class="content-conclusion"><hr> <p>&nbsp;</p> <p>Diversity creates a healthier atmosphere: MKS2 Technologies is proud to be an Equal Employment Opportunity / Affirmative Action employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law.</p></div>