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Staff FPGA Engineer at Freeform

Los Angeles, CA (On-site)Full-timeSoftware Engineering Posted 27 days ago
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About the Role

<h2><span style="font-size: 14pt;">STAFF FPGA ENGINEER</span></h2> <p class="x_MsoNormal"><span data-olk-copy-source="MessageBody">Freeform builds AI-native manufacturing systems that unify software, hardware, and physics to produce industrial-scale parts at the speed of human ideation. By treating manufacturing as a single integrated system, we unlock a new era of innovation where complex hardware is designed, built, and scaled without limits.</span></p> <p><span data-contrast="auto">As a Staff FPGA Engineer at Freeform, you will be responsible for architecting and implementing a custom compute platform that enables the world’s first AI-driven, intelligent metal 3D printing technology. You will use the latest and greatest in FPGA’s including the Xilinx Zynq Ultrascale+ MPSoC to scale a high-throughput, low latency image processing pipeline. You will also have an opportunity to integrate your FPGA solutions with state-of-the-art GPUs to create an advanced machine learning acceleration platform. You will drive interdisciplinary engineering efforts between software, electrical, and process engineering teams to rapidly innovate custom FPGA solutions. High-performance computing to central to what makes Freeform’s technology unique and powerful, so this is a high-impact role in which you’ll develop core IP for a world-changing technology.</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></p> <p><span data-contrast="auto">3D printing experience is not required to be successful here - rather we look for smart, motivated, collaborative engineers who love solving hard problems and creating amazing technology!</span></p> <p><iframe src="https://www.youtube.com/embed/sXfG6ssZ190" width="560" height="314"></iframe></p> <p><strong>Responsibilities:</strong></p> <ul> <li><span data-contrast="auto">Architect and implement FPGA solutions to scale a high-throughput, ultra-low latency image processing pipeline&nbsp;</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Lead interdisciplinary efforts between software, electrical, and process engineering to drive innovation on FPGA capabilities</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Architect and implement&nbsp;custom FPGA capabilities to enable real-time machine learning</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Architect and implement new logic components for use on FPGAs</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Implement custom algorithms on FPGAs for signal processing</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Implement custom controllers on FPGAs</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> </ul> <p>&nbsp;<strong>Basic Qualifications:</strong></p> <ul> <li><span data-contrast="auto">Bachelor’s degree in computer engineering, electrical engineering, computer science, or related field</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">10+ years of FPGA development experience in SystemVerilog or VHDL</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Familiarity with Xilinx Vivado/Vitis toolchain development environment</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li>Experience with high-speed IO, board bring up, and similar hardware-centric FPGA development domains</li> </ul> <p><strong>Nice to Have:</strong></p> <ul> <li><span data-contrast="auto">Master’s degree in computer engineering, electrical engineering, computer science, or related field</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">Experience with image processing or DSP</span></li> <li><span data-contrast="auto">Experience with Xilinx Zynq Ultrascale+ MPSoC</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Experience with embedded software development including embedded Linux and System on Chip (SoC)-based architectures</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Experience implementing math/advanced computations on FPGAs</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Experience with heterogeneous computing platforms and high-speed data acquisition systems</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Familiarity with C/C++ or other high-level programming languages</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Excellent verbal and written communication skills</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">Creative thinker able to apply first-principles reasoning to solve complex problems</span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> </ul> <p><strong>Location:</strong></p> <ul> <li> <p>Based in Hawthorne, our vertically integrated facility brings technology development, R&amp;D, and production together under one roof. We operate at the center of LA’s deep tech ecosystem, surrounded by some of the most ambitious hardware innovation happening anywhere in the country.</p> <span data-teams="true"><span id="message-body-1771454273221" class="fui-ChatMessage__body r7802u9 ___vfhe6q0 f10pi13n ftqa4ok f2hkw1w f8hki3x f1d2448m f1bjia2o ffh67wi f1j6vpng f1pniga2 f987i1v f1ffjurs f15bsgw9 f14e48fq f18yb2kv fd6o370 ffwy5si f3znvyf f57olzd f4stah7 f480a47 fs1por5 fk6fouc figsok6 fkhj508 f19n0e5 f9ijwd5 ffzz00n f1ozlkrg f1o0qvyv f9ggezi f1xp5gbu f150uoa4 ffyari3 f16xq7d1 fo7qwa0 fxowb0n f11ghf3q f13aoclr flypziy f10kwr27 fquw1qa fftr39l f13lathq f15hsm81 f2ss68y ffb60jq f8nuap2 f13nk4fk f7jacry fq08z5q fd9af6s fr74w9q fcl9uv6 f13sm7pj f1u6qqly f16wpxbl faim3u9 f6cs3qo fa2w2z3 fd39nx6 f10gn8j9 frcqmxy f1w9ws4k f1ddxkqj fd10euv fvuz61 f1nbc6gw"><span id="content-1771454273221" class="fui-Primitive ___11tzqds f1oy3dpc f89hs3r fqtknz5 fyvcxda"></span></span></span></li> <li> <p>Our fast-paced, cross-functional environment is built on close collaboration, and as such, this role requires full-time onsite presence (five days a week), with very limited exceptions.</p> <span data-teams="true"><span id="content-1776896507672" class="fui-Primitive ___11tzqds f1oy3dpc f89hs3r fqtknz5 fyvcxda"></span></span></li> </ul> <p><strong>What We Offer:</strong></p> <ul> <li>We have an inclusive and diverse culture that values collaboration, learning, and making deliberate data-driven decisions.</li> <li>We offer a unique opportunity to be an early and integral member of a rapidly growing company that is scaling a world-changing technology.</li> <li>Benefits <ul> <li>Significant stock option packages</li> <li>100% employer-paid Medical, Dental, and Vision insurance (premium PPO and HMO options)</li> <li>Life insurance</li> <li>Traditional and Roth 401(k)</li> <li>Relocation assistance provided</li> <li>Paid vacation, sick leave, and company holidays</li> <li>Generous Paid Parental Leave and extended transition back to work for the birthing parent</li> <li>Free daily catered lunch and dinner, and fully stocked kitchenette</li> <li>Casual dress, flexible work hours, and regular catered team building events</li> </ul> </li> <li>Compensation &nbsp; <ul> <li><span data-contrast="auto">As a growing company, the salary range is intentionally wide as we determine the most appropriate package for each individual taking into consideration years of experience, educational background, and unique skills and abilities as demonstrated throughout the interview process. Our intent is to offer a salary that is commensurate for the company’s current stage of development and allows the employee to grow and develop within a role. </span><span data-ccp-props="{&quot;201341983&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></li> <li><span data-contrast="auto">In addition to the significant stock option package, the estimated salary range for this role is $150,000-$400,000<span data-teams="true">. The upper end of the range is reserved for individuals who demonstrate exceptional experience, deep domain mastery, and a proven history of high performance and impact.</span></span></li> </ul> </li> <li>Freeform is an Equal Opportunity Employer that values diversity; employment with Freeform is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.</li> </ul>

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