Senior Staff Electrical Engineer at CHAOS Industries

El Segundo, California, United StatesFull-timeEngineering Posted 8 days ago

About the Role

CHAOS Industries is redefining modern defense with a multi-product portfolio that gives the ultimate advantage—domain dominance. The company's products are powered by Coherent Distributed Networks (CDN™), empowering warfighters, commercial air operators, and border protection teams to act faster, adapt rapidly, and stay ahead of evolving threats.  CHAOS Industries was founded in 2022 and has raised a total of $1 billion in funding from leading investors, including 8VC, Accel, and Valor Equity Partners. The company is headquartered in Los Angeles, with offices in Washington, D.C., San Francisco, San Diego, Seattle, and London. For more information, please visit <a href="https://www.chaosinc.com">www.chaosinc.com</a>. Role Overview:  CHAOS is seeking a Senior Staff Electrical Engineer with expertise in digital circuit design and signal integrity analysis to provide senior technical leadership for high-reliability digital electronics used in aerospace and military applications. This role spans the full product lifecycle, from early architecture and requirements shaping through detailed design, analysis, verification, production support, and fielded system sustainment.  The ideal candidate is an experienced digital hardware technical leader with deep high-speed board design, signal integrity, and power integrity expertise; a track record of leading complex designs and influencing technical direction; and the ability to guide cross-disciplinary teams through ambiguous, high-consequence hardware challenges.  This is a full-time, on-site position in El Segundo, CA.    Responsibilities:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Lead the design and technical execution of high-speed digital circuit cards and subsystems in accordance with customer requirements, applicable aerospace and military standards, and internal design practices </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Lead design and review of complex PCBAs involving FPGAs, processors, memory devices, data converters, clocks, high-speed serial interfaces, and mixed-signal boundaries </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Lead digital hardware architecture trades and define design approaches that balance system performance, schedule, manufacturability, reliability, and qualification requirements </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Develop and promote design practices for digital board design, stack-up definition, layout constraints, SI/PI analysis, bring-up, and verification within assigned product areas </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Resolve complex cross-disciplinary technical issues involving digital hardware, FPGA/software interfaces, RF coexistence, power distribution, EMI/EMC, thermal behavior, and mechanical packaging </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Define and review PCB layout strategy for controlled impedance, length matching, return paths, grounding, shielding, decoupling, power distribution networks, and isolation of sensitive circuits </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Serve as a senior technical interface with customers, vendors, suppliers, and internal program leadership for digital hardware topics </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Mentor engineers and coordinate technical activities across digital, FPGA, embedded software, RF, power, mechanical, manufacturing, and test teams </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Lead or provide technical direction for hardware integration, verification, qualification testing, production transition, failure analysis, and field support </li> </ul>   Minimum Requirements:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Bachelor's degree in Electrical Engineering with 12+ years of relevant engineering experience </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Demonstrated technical leadership of complex high-speed digital hardware designs </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Strong understanding of digital design fundamentals, including timing, clocking, controlled impedance, signal integrity, power integrity, grounding, decoupling, and return-path management </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Extensive experience with digital board design involving FPGAs, processors, memory devices, high-speed data converters, and board-level communication interfaces </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Experience defining or reviewing PCB layout strategy, design constraints, and analysis criteria for high-speed digital, mixed-signal, and high-reliability electronics </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Hands-on experience leading or supporting board bring-up, system integration, troubleshooting, verification, qualification, production transition, and failure analysis activities </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Demonstrated ability to lead technical execution and mentor engineers through ambiguous, cross-disciplinary hardware challenges </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Ability to obtain and maintain a U.S. security clearance </li> </ul>   Preferred Requirements:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Advanced Degree (MS or PhD) in Electrical Engineering, Systems Engineering, Physics, Mathematics or related discipline </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Experience with Avionics platforms </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1">Experience using Altium Designer </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1">Expertise with signal integrity and/or power integrity analysis tools such as HyperLynx, Sigrity, ADS, Ansys SIwave, or equivalent </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="12" data-aria-level="1">Experience with DDR, PCIe, Ethernet, JESD204, SERDES, LVDS, or similar high-speed interfaces in high-reliability systems </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1">Familiarity with EMI/EMC mitigation techniques and aerospace standards such as RTCA/DO-160, MIL-STD-461, MIL-STD-810, and MIL-STD-1275 </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1">Experience developing design standards, analysis templates, qualification approaches, or review processes for engineering teams </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="15" data-aria-level="1">Experience designing for manufacturability and leading transition from prototype hardware to production </li> </ul> Why CHAOS? <ul> <li>Health Benefits: Medical, dental, and vision benefits 100% paid for by the company</li> <li>Additional benefits: 401k (+ 50% company match up to 6% of pay), FSA, HSA, life insurance, and more</li> <li>Our Perks: Free daily lunch, ‘No meeting Fridays’, unlimited PTO, casual dress code</li> <li>Compensation Components: Competitive base salaries, generous pre-IPO stock option grants, relocation assistance, and (coming soon!) annual bonuses</li> <li>Team Growth: 250 employees and counting across 5 global offices</li> </ul> <div>$211k-264k</div> The stated compensation range reflects only the targeted base compensation range and excludes additional earnings such as bonus, equity, and benefits. If your compensation requirements fall outside of the range, we still encourage you to apply. The salary range for this role is an estimate based on a range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations.    <hr> <h3>Recruiting Agencies: CHAOS Industries does not accept unsolicited resumes or outreach. Unsolicited submissions will not be reviewed or compensated.</h3> <hr>   #LI-onsite

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