Principal Photonics Package Architect at Astera Labs

San Jose, California, United StatesFull-timeSignal Connectivity GroupPosted 2 months ago

About the Role

<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div>Location: San Jose, CA (On-site).  About the Role  Astera Labs is seeking a Principal Photonics Package Architect to define and drive package architecture for next-generation photonics products for scale up and scale out AI infrastructure applications. This is a high-impact senior individual contributor role focused on aligning electrical, thermal, and mechanical design requirements across functions, enabling robust package implementation, and guiding package technology decisions for NPO and CPO products.  Responsibilities  <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="1" data-aria-level="1">Define photonics package architecture, define electrical and optical interface specifications, and establish signal integrity and power integrity requirements. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="2" data-aria-level="1">Establish and manage Thermal Design Power (TDP) budgets and thermal performance targets. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="3" data-aria-level="1">Drive cross-functional alignment with EIC, PIC, and hardware teams on co-design constraints and drive system optical link budget. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="4" data-aria-level="1">Partner with validation, test, and reliability teams to define DFT and DFR requirements and acceptance criteria. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="5" data-aria-level="1">Finalize bump map and ball map, and manage ECOs and revision control of package design databases. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="6" data-aria-level="1">Lead package-level design reviews and own the package design technical roadmap. </li> </ul> Basic Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="7" data-aria-level="1">B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="8" data-aria-level="1">10+ years of experience in semiconductor or photonics package development, package design, or package integration, with demonstrated technical leadership. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="9" data-aria-level="1">Strong understanding of package architecture tradeoffs across electrical, optical, thermal, mechanical, and manufacturability considerations. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="10" data-aria-level="1">Experience working across chip, board, and system-level design electrical and optical interfaces in complex product development environments. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="11" data-aria-level="1">Experience with package EDA tools and electrical simulation tools, including Cadence APD+ and Ansys HFSS. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="12" data-aria-level="1">Experience with advanced packaging design, including 2.5D and 3D package architectures. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="13" data-aria-level="1">Familiarity with package design flows, design database management, and engineering change control practices. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="14" data-aria-level="1">Ability to drive technical decisions, resolve cross-functional issues, and communicate architecture direction clearly to stakeholders. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="15" data-aria-level="1">Strong foundation in design reviews, risk assessment, and design quality from concept through production release. </li> </ul> Preferred Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="16" data-aria-level="1">Experience with industry-standard optical interfaces and interconnect technologies relevant to package design. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="17" data-aria-level="1">Experience with advanced photonics packaging technologies for data center interconnects. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="18" data-aria-level="1">Experience supporting package bring-up and correlating design assumptions with validation results. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="19" data-aria-level="1">Experience supporting cross-functional design closure with silicon, photonics, board, validation, test, and reliability teams. </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"singleLevel"}" data-aria-posinset="20" data-aria-level="1">Knowledge of package design for NPO or CPO products. </li> </ul> Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.<div class="content-conclusion">We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</div>

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