Senior ASIC Design Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented<strong> <span class="TextRun Underlined SCXW209305118 BCX0" lang="EN-US" data-contrast="auto"><span class="NormalTextRun SCXW209305118 BCX0">Senior ASIC Design Engineer</span></span>&nbsp;</strong>to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.</p> <p>As a<strong> <span class="TextRun Underlined SCXW209305118 BCX0" lang="EN-US" data-contrast="auto"><span class="NormalTextRun SCXW209305118 BCX0">Senior ASIC Design Engineer</span></span></strong>, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li class="text-start "> <p><strong>Design Ownership &amp; Implementation</strong></p> <ul> <li class="text-start ">Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support</li> <li class="text-start ">Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions</li> <li class="text-start ">Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams</li> </ul> </li> <li class="text-start "> <p><strong>Quality Assurance &amp; Design Optimization</strong></p> <ul> <li class="text-start ">Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient</li> <li class="text-start ">Apply design techniques to meet PPA (Power, Performance, Area) targets</li> <li class="text-start ">Contribute to design quality through verification and validation activities</li> </ul> </li> <li class="text-start "> <p><strong>Methodology Innovation &amp; Collaboration</strong></p> <ul> <li class="text-start ">Participate in design methodology improvements and tool automation initiatives</li> <li class="text-start ">Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter</li> <li class="text-start ">Collaborate effectively across teams to ensure seamless integration</li> </ul> </li> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li class="text-start ">Bachelor's degree in Electrical Engineering or related technical field</li> <li class="text-start ">3+ years of experience in logic design at semiconductor companies</li> <li class="text-start ">Knowledge and experience in Verilog and/or SystemVerilog</li> <li class="text-start ">Excellent communication skills with ability to work effectively across teams</li> <li class="text-start ">Understanding of digital design principles and RTL coding best practices</li> </ul> <p><strong>Preferred Qualifications</strong></p> <ul> <li class="text-start ">Master's degree in Electrical Engineering or related field</li> <li class="text-start ">Knowledge of DDR and PCIe protocols and implementation</li> <li class="text-start ">Understanding of power management techniques for low-power design</li> <li class="text-start ">Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis</li> <li class="text-start ">Proficiency in scripting languages such as Python or Perl</li> <li class="text-start ">Experience with high-speed serial interface designs or connectivity protocols</li> </ul><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>