Senior/ Staff Front-End CAD Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p><span data-contrast="none"><span class="EOP SCXW38165641 BCX0" data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;335559738&quot;:0,&quot;335559739&quot;:160}">Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, </span></span>we're seeking a highly skilled<strong> Front-End CAD Engineer&nbsp;</strong>to join our local engineering powerhouse from the ground up.</p> <p data-path-to-node="4"><span data-teams="true">As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.</span></p> <p><strong><span data-contrast="none"><br>Key Responsibilities</span></strong></p> <p></p> <ul> <li>Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes</li> <li>Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows</li> <li>Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics</li> <li>Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows</li> </ul> <p></p> <p><strong><span data-contrast="none"><br></span>Basic Qualifications</strong></p> <ul> <li data-path-to-node="8,0,0">Bachelor’s degree in Electrical Engineering or a related technical field</li> <li data-path-to-node="8,1,0">5+ years of hands-on professional experience in relevant industries&nbsp;</li> <li data-path-to-node="8,1,0">Proven experience in&nbsp;<strong>Python</strong> and <strong>Tcl</strong> within a Linux/Unix environment</li> <li data-path-to-node="8,1,0">Knowledge and experience in Verilog and/or System Verilog</li> <li data-path-to-node="8,1,0">Very good communication skills</li> </ul> <p></p> <p><strong><span data-contrast="none">Preferred Experience</span></strong></p> <p></p> <ul> <li>Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis</li> <li>Hands-on experience with industry-standard tools for lint, synthesis, simulation</li> <li>Experience with version control systems (Git) and compute cluster management (LSF/SGE)</li> </ul> <p></p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>