Senior FPGA Engineer at Epirus
Torrance, California, United StatesFull-timeEngineeringPosted about 1 month ago
Apply with PipelineAbout the Role
<p> </p>
<h2><strong><span data-contrast="auto">About Epirus </span></strong><span data-ccp-props="{}"> </span></h2>
<p><span class="NormalTextRun CommentStart CommentHighlightPipeRestV2 CommentHighlightRest SCXW6194141 BCX8">E</span><span class="NormalTextRun CommentHighlightPipeRestV2 SCXW6194141 BCX8">pirus is a high-growth technology company dedicated to overcoming the asymmetric challenges inherent to the future of national security. Epirus' flagship product, Leonidas, is a software-defined system built using intelligent power management techniques which allow power-hungry systems to do more with less.</span></p>
<p><strong><span data-contrast="auto">Job objective: </span></strong><span data-contrast="auto"><span class="TextRun SCXW124030239 BCX0" lang="EN" data-contrast="none"><span class="NormalTextRun SCXW124030239 BCX0">This is an exciting role an innovative, high-growth defense technology company. </span></span><span class="TextRun SCXW124030239 BCX0" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW124030239 BCX0">The ideal candidate for the position is someone who has experience designing, verifying, and integrating </span><span class="NormalTextRun SCXW124030239 BCX0">state-of-the-art</span><span class="NormalTextRun SCXW124030239 BCX0"> FPGA systems and embedded processing solutions for RF applications. </span><span class="NormalTextRun SCXW124030239 BCX0">As a </span><span class="NormalTextRun CommentStart SCXW124030239 BCX0">Sr.</span><span class="NormalTextRun SCXW124030239 BCX0"> FPGA Engineer</span><span class="NormalTextRun SCXW124030239 BCX0">, you will work closely with a talented, multi-disciplinary engineering team in a fast-paced environment to apply emerging technologies in innovative ways to rapidly produce new products</span><span class="NormalTextRun SCXW124030239 BCX0">. </span><span class="NormalTextRun SCXW124030239 BCX0"> </span></span></span><span class="EOP SCXW124030239 BCX0" data-ccp-props="{}"> </span></p>
<h2><strong><span data-contrast="auto">Duties </span></strong><span data-ccp-props="{}"> </span></h2>
<ul>
<li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Design and verification of RTL modules for FPGA applications</span></li>
<li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Ownership of entire FPGA designs from initial architecture trades through implementation, verification, and hardware bringup, including FPGA sizing estimation and IO planning.</li>
<li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Lead initial testing and bring-up of custom FPGA circuit cards, validating functionality of on-board peripherals including memory interfaces, Ethernet controllers, and integrated sensors.</li>
<li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Automating test environment (up to and including hardware-in-the-loop testing), lab equipment, and measurement devices</li>
<li data-leveltext="●" data-font="Arial" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Capturing design tradeoffs, state machine flow, system address maps, and block diagrams<span data-ccp-props="{"201341983":0,"335557856":16777215,"335559740":343}"> </span></li>
</ul>
<h2><strong><span data-contrast="auto">Required Qualifications </span></strong><span data-ccp-props="{}"> </span></h2>
<ul>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Bachelor’s degree in Electrical Engineering or a related field.</span></li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">5+ years of experience <span data-contrast="auto">in FPGA design, implementation, and testing</span></li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Extensive experience implementing FPGA designs and embedded processing designs on embedded hardware</li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience working with latest generation state-of-the-art Xilinx/Intel Parts and associated tool sets (Vivado, Quartus)</li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Understanding of common digital communication protocols (SPI, I2C, UART)</li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Development Experience of Integrated Embedded Applications (ARM, GPU)</li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience with standard bus and streaming protocols, such as AXI and AXI-Stream</li>
<li data-leveltext="●" data-font="" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience with Continuous Integration and Continuous Delivery processes</li>
<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Active Secret or Top Secret clearance, or ability to obtain one desired but not required. </span><span data-ccp-props="{}"> </span></li>
</ul>
<h2><strong><span data-contrast="auto">Desired Qualifications </span></strong> </h2>
<ul>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Experience with design automation, scripting languages (TCL, Python, Perl, Matlab)</span></li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Knowledge of Advanced Firmware Verification Testbench Development (UVM, System Verilog)</li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Skilled with Advanced High-Speed Verilog/VHDL Designs including High Speed Memory Interfaces (DDR4, HBM) and High Speed SerDes IO and Protocols (100GE, JESD204B, Interlaken)</li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience implementing Complex DSP Algorithms on FPGAs using tools such as Matlab, Simulink, HDL Coder to implement advanced communications or other designs in FPGA</li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Experience collaborating with software engineering team in an SoC environment to develop designs that incorporate HDL combined with embedded Linux</li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Good written and oral communication skills</li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Collaborative; capable of working across all levels of the organization</li>
<li data-leveltext="●" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559682":2,"335559685":720,"335559991":360,"469769242":[8226],"469777803":"left","469777804":"●","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Organized; comfortable working in a fast-paced, ever-changing environment<span data-ccp-props="{"201341983":0,"335557856":16777215,"335559740":335}"> </span></li>
</ul>
<div>
<p> </p>
<p><strong>ITAR REQUIREMENTS:</strong> </p>
<ul>
<li>To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR <a href="https://www.pmddtc.state.gov/ddtc_public/ddtc_public?id=ddtc_kb_article_page&sys_id=24d528fddbfc930044f9ff621f961987" target="_blank">here</a>. </li>
</ul>
<p><span class="TextRun SCXW223840355 BCX8" lang="EN-US" data-contrast="auto"><span class="NormalTextRun SCXW223840355 BCX8">At Epirus, </span><span class="NormalTextRun SCXW223840355 BCX8">you’ll</span><span class="NormalTextRun SCXW223840355 BCX8"> work with technical peers and great people—and get first crack at some of the defining technology challenges of our time. Here, “impossible” is just a challenge. </span></span><span class="TextRun SCXW223840355 BCX8" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW223840355 BCX8">We're</span><span class="NormalTextRun SCXW223840355 BCX8"> a diverse, fast-growing team of change-makers fueling the future of energy with revolutionary solutions. </span></span><a class="Hyperlink SCXW223840355 BCX8" href="https://www.epirusinc.com/open-roles" target="_blank"><span class="TextRun Underlined SCXW223840355 BCX8" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW223840355 BCX8" data-ccp-charstyle="Hyperlink">Join us and rewrite the rules.</span></span></a><span class="EOP SCXW223840355 BCX8" data-ccp-props="{"201341983":0,"335559740":240}"> </span></p>
</div>
<p> </p>
<p> </p><div class="content-pay-transparency"><div class="pay-input"><div class="description"><em data-stringify-type="italic">As required by the Equal Pay Transparency Act, Epirus provides a reasonable range of minimum compensation for roles that may be hired. Actual compensation is influenced by a wide array of factors including but not limited to skill set, level of experience, and specific office location. </em></div><div class="title">For the state of California only, the range of starting pay for this role is: </div><div class="pay-range"><span>$142,800</span><span class="divider">—</span><span>$175,600 USD</span></div></div></div>
Related Roles
Senior Software Engineer, Integration and Test
Epirus
Torrance, California, United StatesPrincipal Software Engineer
Epirus
Torrance, California, United StatesSenior RF Engineer (Contract) - Future Opportunities
Epirus
Torrance, California, United StatesPrincipal System Engineer (Contract)
Epirus
Torrance, California, United StatesSenior Systems Engineer- Development
Epirus
Torrance, California, United StatesManager, Warehouse Inventory Control
Epirus
Torrance, California, United States