Senior/ Staff Physical Design STA Engineer at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled <strong>Static Timing Analysis (STA) Engineer </strong>to join our local engineering powerhouse from the ground up.</p> <p data-path-to-node="4">This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.</p> <p></p> <p><strong><span data-contrast="auto">Key Responsibilities</span></strong></p> <p><span data-contrast="none"></span></p> <ul> <li data-path-to-node="6,0,0">Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments</li> <li data-path-to-node="6,1,0">Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence</li> <li data-path-to-node="6,2,0">Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments</li> <li data-path-to-node="6,3,0">Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners</li> <li data-path-to-node="6,4,0">Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient</li> </ul> <p><span data-contrast="none"></span></p> <p><strong>Basic Qualifications</strong></p> <p><span data-contrast="none"></span></p> <ul> <li data-path-to-node="8,0,0">B.Sc. in Electrical Engineering or Computer Engineering</li> <li data-path-to-node="8,1,0">5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. <em data-path-to-node="8,1,0" data-index-in-node="147">(Note: Adjust years of experience based on the exact level you are targeting)</em></li> <li data-path-to-node="8,2,0">Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels</li> <li data-path-to-node="8,3,0">Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off</li> <li data-path-to-node="8,4,0">Solid knowledge of physical design flows (Synthesis, P&amp;R, Physical Verification) and how they intersect with timing closure</li> </ul> <p><span data-contrast="none"></span></p> <p><strong><span data-contrast="none">Preferred Experience</span></strong></p> <p><span data-contrast="none"></span></p> <ul> <li data-path-to-node="10,0,0">Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)</li> <li data-path-to-node="10,1,0">Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration</li> <li data-path-to-node="10,2,0">Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency</li> </ul> <p><span data-contrast="none"></span></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>