Senior Digital Design Engineer at Astera Labs

Toronto, Ontario, CanadaFull-timeSilicon Engineering SCEPosted 26 days ago

About the Role

<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div>Role Overview  <span data-ccp-parastyle="First Paragraph" data-ccp-parastyle-defn="{"ObjectId":"276295ed-5df2-5456-988c-5fdbab071054|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"180",335559738,"180",469775450,"First Paragraph",201340122,"2",134234082,"true",134233614,"true",469778129,"FirstParagraph",335572020,"1",469775498,"Body Text",469778324,"Body Text"]}">As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces.  You will work with cross-functional teams to turn complex connectivity requirements into robust, production-ready designs. Your work will span block-level and full-chip development at advanced process nodes and help enable reliable, high-bandwidth connections among CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems. You will help improve product quality, accelerate time to market, and strengthen customer confidence in every release.  Key Responsibilities  <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="1">Digital Architecture and RTL Implementation </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-ccp-parastyle="Compact" data-ccp-parastyle-defn="{"ObjectId":"eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"36",335559738,"36",469775450,"Compact",201340122,"2",134234082,"true",134233614,"true",469778129,"Compact",335572020,"1",469778324,"Body Text"]}">Develop micro-architecture and implement synthesizable RTL for high-performance PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2">Translate architecture and protocol requirements into scalable designs using SystemVerilog and Verilog. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2">Own block-level and full-chip design deliverables from specification through implementation and GDS handoff. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2">Contribute to designs at advanced process nodes of 16 nm or smaller, including PCIe Gen 6/7, UALink, or UCI-based connectivity where applicable. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Integration, Timing, and Design Quality </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2">Integrate controller, SerDes, processor, peripheral, and other IP while partnering with RTL, physical design, DFT, verification, and firmware teams. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2">Drive synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2">Support gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2">Contribute to top-level integration, floor-planning discussions, PAD planning, and DFT implementation. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">Cross-Functional Execution and Debug </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2">Collaborate with verification and system teams to assess verification completeness, debug design issues, and close implementation gaps. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2">Partner with firmware and embedded software teams to define and validate hardware-software interfaces. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2">Use Synopsys and Cadence design and analysis tools, along with Python or Perl scripting, to improve design productivity and automation. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2">Communicate technical status, risks, and tradeoffs clearly while managing multiple priorities with appropriate ownership and urgency. </li> </ul> Basic Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1">Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1">2 - 5 years of experience in digital design and implementation for complex SoC or silicon products. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1">Hands-on experience developing RTL in SystemVerilog or Verilog, including synthesis and timing closure. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1">Experience with PCIe or Ethernet controller, bridge, switch, PCS, PHY, or SerDes design and IP integration. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1">Experience with front-end design, gate-level simulation, clock-domain crossing, lint, or related design-quality methodologies. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="8" data-aria-level="1">Experience using Python or Perl to automate design, integration, or analysis workflows. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="9" data-aria-level="1">Ability to collaborate effectively across design, verification, physical design, DFT, firmware, and system teams. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="10" data-aria-level="1">Authorized to work in Canada. </li> </ul> Preferred Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="11" data-aria-level="1">Experience with PCIe or Ethernet SerDes controller or IP-level design, including PCIe Gen 6/7, UALink, or UCI. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="12" data-aria-level="1">Experience with block-level and full-chip implementation at advanced process nodes of 16 nm or smaller. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="13" data-aria-level="1">Knowledge of PAD design, DFT, floor planning, and top-level integration. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="14" data-aria-level="1">Experience developing NIC, switch, storage, or other high-performance connectivity products with embedded firmware interaction. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="15" data-aria-level="1">Familiarity with continuous integration and continuous delivery workflows for design and verification. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="16" data-aria-level="1">Experience with FPGA-based prototyping, emulation, or post-silicon debug. </li> </ul> Salary range is $139,500 to $155,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.   <div class="content-conclusion">We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</div>

About the Role

Related Roles