Digital Design Manager at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">&nbsp;</p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Role Overview</strong></p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This role will lead day-to-day DFT architecture and execution for Astera Labs' signal-conditioning products, helping deliver highly testable, high-quality silicon for rack-scale AI infrastructure. You will partner with design, verification, physical design, packaging, product engineering, and manufacturing teams to improve coverage, yield, diagnostics, and production readiness across advanced multi-die products.</p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">As Astera Labs scales its purpose-built connectivity platform, you will help establish practical DFT methods for high-speed PCIe and Ethernet signal-conditioning products, with a strong focus on SerDes physical-layer performance, signal integrity, and production robustness. The role offers hands-on technical ownership, opportunities to mentor engineers, and direct influence on products that keep next-generation AI systems connected, observable, and reliable.</p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Key Responsibilities</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>DFT Architecture &amp; Planning</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Define DFT plans for signal-conditioning products supporting high-speed PCIe and Ethernet connectivity and advanced multi-die packaging configurations.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Partner with design and physical design teams to balance DFT area, timing, routing, and manufacturability.</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>DFT Implementation &amp; Silicon Readiness</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Establish coverage targets and review ATPG results, pattern quality, test time, and ATE cost.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Quality, Yield &amp; Diagnostics</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Improve diagnostic capabilities for silicon, package, and system-level issues.</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Technical Leadership &amp; Collaboration</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Mentor DFT engineers and coordinate execution across product development milestones.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders to resolve technical issues and maintain schedules.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Communicate risks, trade-offs, and recommendations clearly to cross-functional teams.</p> </li> </ul> </li> </ul> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Basic Qualifications</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><span data-teams="true">10-15 years of experience in Digital Design engineering or related semiconductor design and test work.</span></p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Understanding of the ASIC design flow from RTL through GDS and DFT signoff.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.</p> </li> </ul> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Preferred Qualifications</strong></p> <ul class="wnfdntf"> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Experience with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Experience with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.</p> </li> <li class="wnfdnte _1ibi0s33w"> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.</p> </li> </ul> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Salary range is CAD $198,000 to CAD $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>