Distinguished Engineer – Server Firmware & System Architecture at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next.</p> <p>The AI Platform Solutions Group is seeking a <strong>Distinguished Engineer</strong> to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers.</p> <p>This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li><strong>AI Platform &amp; Rack-Scale Architecture</strong></li> <ul> <li>Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems</li> <li>Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability</li> <li>Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads</li> <li>Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem</li> </ul> </ul> <ul> <li><strong>Firmware &amp; Platform Leadership</strong></li> <ul> <li>Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks</li> <li>Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms</li> <li>Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms</li> </ul> </ul> <ul> <li><strong>Performance &amp; Optimization</strong></li> <ul> <li>Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads</li> <li>Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies</li> <li>Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads</li> </ul> </ul> <ul> <li><strong>Ecosystem &amp; Industry Leadership</strong></li> <ul> <li>Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers</li> <li>Influence industry standards across OpenBMC, Redfish, OCP, and related consortia</li> <li>Mentor senior engineers and grow deep technical bench strength across the organization</li> <li>Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation</li> </ul> </ul> <p><strong>Basic Qualifications</strong></p> <ul> <li>Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field</li> <li>15+ years of experience in system architecture, server firmware, or platform engineering</li> <li>Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks</li> <li>Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6)</li> <li>Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms</li> <li>Strong programming experience in C/C++ and low-level system software</li> <li>Proven track record of leading cross-functional, large-scale architecture initiatives</li> </ul> <p><strong>Preferred Qualifications</strong></p> <ul> <li>Master's degree or PhD in Computer Science, Electrical Engineering, or a related field</li> <li>Experience with rack-scale composable infrastructure and disaggregated architectures</li> <li>Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design</li> <li>Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs</li> <li>Experience with platform lifecycle management systems and fleet-level automation</li> <li>Contributions to industry standards bodies or open-source firmware ecosystems</li> <li>Demonstrated ability to define multi-year technical roadmaps and influence executive strategy</li> </ul> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>