Principal Emulation Engineer at Astera Labs

San Jose, California, United StatesFull-timeAdvanced DV & Emulation CCE1Posted 28 days ago

About the Role

<div class="content-intro">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</div>Principal Emulation Engineer — San Jose, CA  Role Overview  <span data-ccp-parastyle="First Paragraph" data-ccp-parastyle-defn="{"ObjectId":"276295ed-5df2-5456-988c-5fdbab071054|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"180",335559738,"180",469775450,"First Paragraph",201340122,"2",134234082,"true",134233614,"true",469778129,"FirstParagraph",335572020,"1",469775498,"Body Text",469778324,"Body Text"]}">As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone.  Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role, you’ll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales.  Key Responsibilities  <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="1">Emulation and Prototyping </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-ccp-parastyle="Compact" data-ccp-parastyle-defn="{"ObjectId":"eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"36",335559738,"36",469775450,"Compact",201340122,"2",134234082,"true",134233614,"true",469778129,"Compact",335572020,"1",469778324,"Body Text"]}">Architect, build, and maintain emulation environments for complex ASICs and SoCs. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2">Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2">Enable verification teams to stress-test designs with scalable, repeatable emulation workflows. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2">Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Protocol and SoC Verification </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2">Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2">Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe, SPI, I2C/I3C, and similar interfaces. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2">Analyze protocol behavior, functional coverage, performance, and corner cases across complex server, storage, and networking systems. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2">Translate system requirements into practical emulation scenarios, tests, checkers, and measurable verification goals. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">Debug and Technical Leadership </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2">Debug design, environment, transactor, software, and test-code issues across the emulation stack. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2">Identify software and hardware co-simulation limitations and apply effective isolation and debug techniques. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2">Partner with cross-functional teams to prioritize a dynamic workload, resolve issues quickly, and drive risks to closure. </li> </ul> <ul> <li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2">Provide technical leadership, communicate clearly, and operate effectively with minimal guidance and supervision. </li> </ul> Basic Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1">Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1">8–12 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1">Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1">Working knowledge of PCI Express Gen 3 or later, CXL, UALink, Ethernet, DDR, NVMe, SPI, I2C/I3C, or similar communication protocols. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1">High proficiency in SystemVerilog and hardware verification environments. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="8" data-aria-level="1">Experience understanding software and hardware co-simulation limitations and applying effective debug methods. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="9" data-aria-level="1">Programming and scripting experience in Python, Perl, C, or similar languages. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="10" data-aria-level="1">Professional, entrepreneurial, and open-minded approach with a can-do attitude, strong prioritization skills, and a customer-focused mindset. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="11" data-aria-level="1">Authorized to work in the United States and available to start immediately. </li> </ul> Preferred Qualifications  <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="12" data-aria-level="1">Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="13" data-aria-level="1">Hands-on experience with Palladium, Zebu, Veloce, HAPS, FPGA prototyping, or similar emulation and prototyping technologies. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="14" data-aria-level="1">Experience developing models for emulation and prototyping and working in non-UVM verification environments. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="15" data-aria-level="1">Experience building protocol transactors, behavioral models, software drivers, or system-level validation infrastructure. </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="16" data-aria-level="1">Based in the San Jose area or open to relocation; comfortable working fully in person. </li> </ul> Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.   <div class="content-conclusion">We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</div>

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