Senior/ Staff Physical Design CAD Engineer - Automation & Signoff at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p><span data-contrast="none"><span class="EOP SCXW38165641 BCX0" data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;335559738&quot;:0,&quot;335559739&quot;:160}">Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, </span></span>we're seeking a highly skilled <strong>Physical Design CAD Engineer</strong> specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.</p> <p data-path-to-node="4">This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.</p> <p><strong><span data-contrast="none"><br>Key Responsibilities</span></strong></p> <p><span data-contrast="none"></span></p> <ul> <li data-path-to-node="6,0,0">Develop and maintain automated flows for Synthesis, Place &amp; Route (P&amp;R), and Floor-planning to ensure seamless design transitions</li> <li data-path-to-node="6,1,0">Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)</li> <li data-path-to-node="6,2,0">Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints</li> <li data-path-to-node="6,3,0">Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations</li> <li data-path-to-node="6,4,0">Own the design database structure and version control to ensure team alignment and data integrity</li> <li data-path-to-node="6,5,0">Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results</li> <li data-path-to-node="6,6,0">Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing</li> </ul> <p><strong><span data-contrast="none"><br></span>Basic Qualifications</strong></p> <p><span data-contrast="none"></span></p> <ul> <li data-path-to-node="8,0,0">Bachelor’s degree in Electrical Engineering or a related technical field</li> <li data-path-to-node="8,1,0">5+ years of hands-on professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus/Innovus)</li> <li data-path-to-node="8,2,0">Expert-level proficiency in <strong>Tcl </strong>and<strong> Python</strong> for high-level flow automation, data parsing, and tool customization</li> <li data-path-to-node="8,3,0">Deep technical understanding of Physical Design concepts, including clock tree synthesis (CTS), routing congestion, timing closure, and signal integrity</li> <li data-path-to-node="8,4,0">Proven experience executing sign-off flows for complex, high-performance designs</li> <li data-path-to-node="8,5,0">Strong communication skills and a collaborative approach to solving complex engineering bottlenecks</li> </ul> <p><span data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;335559738&quot;:0,&quot;335559739&quot;:160}">&nbsp;</span></p> <p><strong><span data-contrast="none">Preferred Experience</span></strong></p> <p><span data-contrast="none"></span></p> <ul> <li data-path-to-node="10,0,0">Hands-on experience with 5nm, 3nm, or more advanced process nodes</li> <li data-path-to-node="10,1,0">Practical knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases</li> <li data-path-to-node="10,2,0">Experience in developing proprietary automation wrappers for industry-standard EDA tools</li> </ul> <p><span data-contrast="none"></span></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>