ASIC Design Student at Astera Labs

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Role Overview</strong></p> <p>Astera Labs is establishing a strategic R&amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary<strong> ASIC Design Student</strong> to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing c<span data-teams="true">omplex solutions</span>&nbsp;that sit at the heart of our most ambitious connectivity projects.</p> <p>As an ASIC Design Student, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.</p> <p>&nbsp;</p> <p><strong>Key Responsibilities</strong></p> <ul> <li data-path-to-node="7,0,0">Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks</li> <li data-path-to-node="7,1,0">Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient</li> <li data-path-to-node="7,2,0">Work closely with the verification team to run simulations, analyze results, and ensure design quality</li> <li data-path-to-node="7,3,0">Interact with Architecture and Backend teams to understand the full chip development lifecycle</li> <li data-path-to-node="7,4,0">Help leverage AI-based automation tools to optimize engineering workflows</li> </ul> <p>&nbsp;</p> <p><strong>Basic Qualifications</strong></p> <ul data-path-to-node="11"> <li data-path-to-node="9,0,0">Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field</li> <li data-path-to-node="9,1,0">Strong academic record with a focus on Digital Logic Design and VLSI</li> <li data-path-to-node="9,2,0">Ability to work at least <strong data-path-to-node="9,2,0" data-index-in-node="39">2 days per week</strong> at our Haifa/Tel Aviv center</li> <li data-path-to-node="9,3,0">Solid understanding of logic design principles and hardware description languages (Verilog or SystemVerilog)</li> <li data-path-to-node="9,4,0">A "can-do" attitude with a passion for solving complex technical challenges</li> <li data-path-to-node="9,5,0">Fluent in Hebrew and English with the ability to work effectively in a team environment</li> </ul> <p>&nbsp;</p> <p><strong>Preferred Qualifications</strong></p> <ul> <li data-path-to-node="11,0,0">Hands-on experience with FPGA projects or university-level tape-out projects</li> <li data-path-to-node="11,1,0">Proficiency in Python, Perl, or Bash for automation</li> <li data-path-to-node="11,2,0">Completed courses in Computer Architecture, Synthesis, or Static Timing Analysis (STA)</li> <li data-path-to-node="11,3,0">Basic familiarity with high-speed protocols like PCIe or DDR</li> </ul> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>