Staff Electrical Engineer at CHAOS Industries

Hawthorne, California, United StatesFull-timeEngineering Posted about 1 month ago

About the Role

CHAOS Industries is redefining modern defense with a multi-product portfolio that gives the ultimate advantage—domain dominance. The company's products are powered by Coherent Distributed Networks (CDN™), empowering warfighters, commercial air operators, and border protection teams to act faster, adapt rapidly, and stay ahead of evolving threats.  CHAOS Industries was founded in 2022 and has raised a total of $1 billion in funding from leading investors, including 8VC, Accel, and Valor Equity Partners. The company is headquartered in Los Angeles, with offices in Washington, D.C., San Francisco, San Diego, Seattle, and London. For more information, please visit <a href="https://www.chaosinc.com">www.chaosinc.com</a>. Role Overview:  CHAOS is seeking a Staff Electrical Engineer with expertise in digital circuit design and signal integrity analysis to lead the design and integration of high-reliability digital electronics for aerospace and military applications. This role spans the full product lifecycle, from requirements definition and architecture trades through schematic design, layout guidance, analysis, board bring-up, verification, production support, and field testing of mission-critical systems.  The ideal candidate is a digital circuit designer with strong hands-on board design experience, practical signal integrity and power integrity judgment, and the ability to coordinate complex technical tasks across FPGA, software, RF, power, mechanical, manufacturing, and test teams with little supervision.  This is a full-time, on-site position in Hawthorne, CA.    Responsibilities:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Lead design of high-speed digital circuit cards and subsystems in accordance with customer requirements, applicable aerospace and military standards, and internal design practices </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Design PCBAs involving FPGAs, processors, memory devices, data converters, clocks, high-speed serial interfaces, and mixed-signal boundaries </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Contribute to digital hardware architectures, detailed schematics, stack-up recommendations, routing constraints, and design analyses for mission-critical electronics </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Perform signal integrity and power integrity analysis for high-speed interfaces, memory buses, clocks, power distribution networks, and mixed-signal board environments </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Define PCB layout constraints for controlled impedance, length matching, return paths, grounding, shielding, decoupling, and isolation of sensitive circuits </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Collaborate with FPGA, embedded software, RF, power, mechanical, manufacturing, and test engineers to ensure digital hardware integrates cleanly within larger systems </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Plan and support board bring-up, integration, troubleshooting, verification, qualification testing, and production transition activities </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Generate and maintain schematics, analysis reports, design documentation, BOMs, interface documentation, and test plans </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1">Serve as a technical interface with vendors, suppliers, and customers for digital hardware design topics </li> </ul>   Minimum Requirements:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Bachelor's degree in Electrical Engineering with 8+ years of relevant engineering experience </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Experience designing high-speed digital hardware  </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Strong understanding of digital design fundamentals, including timing, clocking, controlled impedance, signal integrity, power integrity, grounding, decoupling, and return-path management </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Experience with digital board design involving FPGAs, processors, memory devices, high-speed data converters, and board-level communication interfaces </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Hands-on experience with hardware integration and lab test equipment, including oscilloscopes, logic analyzers, power supplies, and protocol or signal measurement equipment </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Demonstrated ability to work independently on complex technical problems with a high level of attention to detail </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Ability to obtain and maintain a U.S. security clearance </li> </ul>   Preferred Requirements:  <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Advanced Degree (MS or PhD) in Electrical Engineering, Systems Engineering, Physics, Mathematics or related discipline </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Experience with Avionics platforms </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1">Experience using Altium Designer </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1">Experience with mixed RF, analog, power, and digital electronics in tightly integrated aerospace or defense hardware </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1">Experience with DDR, PCIe, Ethernet, JESD204, SERDES, LVDS, or similar high-speed interfaces </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1">Familiarity with EMI/EMC mitigation techniques and aerospace standards such as RTCA/DO-160, MIL-STD-461, MIL-STD-810, and MIL-STD-1275 </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1">Experience performing design margin analysis, derating analysis, tolerance analysis, or worst-case circuit analysis </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":1080,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1">Experience designing for manufacturability and transition to production </li> </ul> Why CHAOS? <ul> <li>Health Benefits: Medical, dental, and vision benefits 100% paid for by the company</li> <li>Additional benefits: 401k (+ 50% company match up to 6% of pay), FSA, HSA, life insurance, and more</li> <li>Our Perks: Free daily lunch, ‘No meeting Fridays’, unlimited PTO, casual dress code</li> <li>Compensation Components: Competitive base salaries, generous pre-IPO stock option grants, relocation assistance, and (coming soon!) annual bonuses</li> <li>Team Growth: 250 employees and counting across 5 global offices</li> </ul> <div>$150k-210k</div> The stated compensation range reflects only the targeted base compensation range and excludes additional earnings such as bonus, equity, and benefits. If your compensation requirements fall outside of the range, we still encourage you to apply. The salary range for this role is an estimate based on a range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations.    <hr> <h3>Recruiting Agencies: CHAOS Industries does not accept unsolicited resumes or outreach. Unsolicited submissions will not be reviewed or compensated.</h3> <hr>   #LI-onsite

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