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Astera Labs

Principal Advanced Packaging Engineer at Astera Labs

Taipei, TaiwanFull-timeEngineering Operations CCE1 (TWN_Engineering Operations CCE1)Posted 23 days ago
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About the Role

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><u>Principal Advanced Packaging Engineer:</u></strong></p> <p><strong>About the Role</strong>&nbsp;</p> <p>Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&amp;D for next-generation packaging technologies for optical chips. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products.&nbsp;</p> <p><strong>Responsibilities</strong>&nbsp;</p> <ul> <li>Lead R&amp;D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.&nbsp;</li> </ul> <ul> <li>Define and&nbsp;optimize&nbsp;wafer-level, panel-level, or die-level packaging process flows.&nbsp;</li> </ul> <ul> <li>Drive EIC-to-PIC integration and broader optical device integration efforts.&nbsp;</li> </ul> <ul> <li>Select and&nbsp;qualify&nbsp;packaging materials for advanced packaging.&nbsp;</li> </ul> <ul> <li>Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.&nbsp;</li> </ul> <ul> <li>Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.&nbsp;</li> </ul> <ul> <li>Develop and&nbsp;maintain&nbsp;packaging&nbsp;PDKs and design rules for NPO and CPO products.&nbsp;</li> </ul> <p><strong>Basic Qualifications:</strong>&nbsp;</p> <ul> <li>B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.&nbsp;</li> </ul> <ul> <li>8+ years of experience in semiconductor or advanced packaging engineering, with&nbsp;demonstrated&nbsp;technical leadership.&nbsp;</li> </ul> <ul> <li>Deep&nbsp;expertise&nbsp;in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and&nbsp;overmold&nbsp;across wafer-, panel-, and die-level flows.&nbsp;</li> </ul> <ul> <li>Experience with silicon&nbsp;photonics&nbsp;chip packaging and EIC/PIC integration.&nbsp;</li> </ul> <ul> <li>Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.&nbsp;</li> </ul> <ul> <li>Proven track record of equipment and process qualification with OSAT or tool suppliers.&nbsp;</li> </ul> <ul> <li>Experience with PDK development and packaging design rule authoring.&nbsp;</li> </ul> <ul> <li>Strong foundation&nbsp;in yield analysis, reliability characterization, and process capability methodologies such as&nbsp;Cpk&nbsp;and SPC.&nbsp;</li> </ul> <p><strong>Preferred Qualifications:</strong>&nbsp;</p> <ul> <li>Hands-on experience with CPO or NPO product development.&nbsp;</li> <li>Experience with optical coupling or waveguide alignment for photonic integration.&nbsp;</li> <li>Familiarity with DFM and DFT for advanced packaging.&nbsp;</li> </ul> <p>Salary range will depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p> <p>&nbsp;</p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>